TAS5548 datasheet(96/120 Pages) TI

96 / 120 page

TAS5548

SLES270 – NOVEMBER 2012

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DAP channel 6 is mapped though the 8×2 crossbar mixer (0xAF) to PWM channel 6

Note that the pass-through output mixer configuration (0xD0 bit 30 = 1) is recommended. Using the

remapped output mixer configuration (0xD0 bit 30 = 0) increases the complexity of using some features

such as volume and mute.

Total data per register is 8 bytes. The default gain for each selected channel is 1 (00 80 00 00) and 0.5

value is (00 40 00 00) value. The format is 5.23

Table 11-34. Output Mixer Register Format (Upper 4 Bytes)

D63

D62

D61

D60

D59

D58

D57

D56

FUNCTION

Select channel 1 to output mixer

Select channel 2 to output mixer

Select channel 3 to output mixer

Select channel 4 to output mixer

Select channel 5 to output mixer

Select channel 6 to output mixer

Select channel 7 to output mixer

Select channel 8 to output mixer

G27

G26

G25

G24

Selected channel gain (upper 4 bits)

D55

D54

D53

D52

D51

D50

D49

D48

FUNCTION

G23

G22

G21

G20

G19

G18

G17

G16

Selected channel gain (continued)

D47

D46

D45

D44

D43

D42

D41

D40

FUNCTION

G15

G14

G13

G12

G11

G10

Selected channel gain (continued)

D39

D38

D37

D36

D35

D34

D33

D32

FUNCTION

Selected channel gain (lower 8 bits)

Table 11-35. Output Mixer Register Format (Lower 4 Bytes)

D31

D30

D29

D28

D27

D26

D25

D24

FUNCTION

Select channel 1 to output mixer

Select channel 2 to output mixer

Select channel 3 to output mixer

Select channel 4 to output mixer

Select channel 5 to output mixer

Select channel 6 to output mixer

Select channel 7 to output mixer

Select channel 8 to output mixer

G27

G26

G25

G24

Selected channel gain (upper 4 bits)

D23

D22

D21

D20

D19

D18

D17

D16

FUNCTION

G23

G22

G21

G20

G19

G18

G17

G16

Selected channel gain (continued)

D15

D14

D13

D12

D11

D10

FUNCTION

G15

G14

G13

G12

G11

G10

Selected channel gain (continued)

FUNCTION

Selected channel gain (lower 8 bits)

Serial-Control Interface Register Definitions

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