LP8556 datasheet(29/52 Pages) TI

29 / 52 page

SCL

3 - 6

Start

Condition

Acknowledgment

Signal From Receiver

Data Output

Receiver

Data Output

Transmitter

Transmitter Stays Off the

Bus During the

Acknowledgment Clock

SDA

SCL

Data Line

Stable:

Data Valid

Change

of Data

Allowed

LP8556

www.ti.com

SNVS871B – JULY 2012 – REVISED SEPTEMBER 2012

2C Compatible Serial Bus Interface

INTERFACE BUS OVERVIEW

The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on

the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected

to the bus. The two interface lines are the Serial Data Line (SDA) and the Serial Clock Line (SCL). These lines

should be connected to a positive supply via a pull-up resistor and remain HIGH even when the bus is idle.

Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on

whether it generates or receives the SCL. The LP8556 can operate as an I2C slave.

DATA TRANSACTIONS

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock SCL.

Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the SDA line

during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New data

should be sent during the low SCL state. This protocol permits a single data line to transfer both

command/control information and data using the synchronous serial clock.

Figure 26. Bit Transfer

Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a

Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is

transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following

sections provide further details of this process.

Figure 27. Start and Stop

The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start

Condition is generated, the bus is considered busy and it retains this status until a certain time after a Stop

Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a

Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition.

Submit Documentation Feedback

Product Folder Links: LP8556

LP8556 Datasheet(PDF) 29 Page - Texas Instruments

LP8556 Datasheet(HTML) 29 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL