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LP8556 Datasheet(PDF) 32 Page - Texas Instruments |
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LP8556 Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 52 page ![]() A/ NA S '0' Slave Address (7 bits) Control Register Add. (8 bits) A A Data- Data (8 bits) P R/W Data transfered, byte + Ack/NAck Sr Slave Address (7 bits) '1' A R/W Direction of the transfer will change at this point From Master to Slave From Slave to Master A - ACKNOWLEDGE (SDA Low) S - START CONDITION P - STOP CONDITION Sr - REPEATED START CONDITION Register Read Format NA - ACKNOWLEDGE (SDA High) S '0' Slave Address (7 bits) Control Register Add. (8 bits) A A A Register Data (8 bits) P R/W From Master to Slave From Slave to Master A - ACKNOWLEDGE (SDA Low) S - START CONDITION P - STOP CONDITION Data transfered, byte + Ack Register Write Format LP8556 SNVS871B – JULY 2012 – REVISED SEPTEMBER 2012 www.ti.com Register Read and Write Detail Figure 30. Register Write Format Figure 31. Register Read Format Table 8. Register Map ADD REGISTER D7 D6 D5 D4 D3 D2 D1 D0 RESET R 00H Brightness BRT[7:0] 0000 Control 0000 01H Device Control FAST BRT_MODE BL_CTL 0000 0000 02H Status OPEN SHORT VREF_OK VBOOST_ OVP OCP TSD UVLO 0000 OK 0000 03H ID PANEL MFG REV 1111 1100 04H Direct Control LED 0000 0000 16H LED Enable LED_EN 0011 1111 Table 9. EPROM Memory Map ADD REGISTER D7 D6 D5 D4 D3 D2 D1 D0 R 98H CFG98 IBOOST_LIM RESERVED RESERVED _2X 9EH CFG9E RESERVED VBOOST_RA RESERVE HEADROOM_OFFSET NGE D A0H CFG0 CURRENT LSB A1H CFG1 PDET_STDB CURRENT_MAX CURRENT MSB Y A2H CFG2 RESERVED UVLO_EN UVLO_TH BL_ON ISET_EN BOOST_FSET PWM_FSET_ _EN EN 32 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LP8556 |
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