ADS4449 datasheet(40/54 Pages) TI

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ADS4449

SBAS603 – APRIL 2013

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APPLICATION INFORMATION

THEORY OF OPERATION

The ADS4449 is a quad-channel, 14-bit, analog-to-digital converter (ADC) with sampling rates up to

250 MSPS. At every falling edge of the input clock, the analog input signal for each channel is sampled

simultaneously. The sampled signal in each channel is converted by a pipeline of low-resolution stages. In each

stage, the sampled-and-held signal is converted by a high-speed, low-resolution, flash sub-ADC. The difference

(residue) between the stage input and quantized equivalent is gained and propagates to the next stage. At every

clock, each subsequent stage resolves the sampled input with greater accuracy. The digital outputs from all

stages are combined in a digital correction logic block and are digitally processed to create the final code, after a

data latency of 10 clock cycles. The digital output is available in a double data rate (DDR) low-voltage differential

signaling (LVDS) interface and is coded in binary twos complement format.

ENABLING 14-BIT RESOLUTION

By default after reset, the ADS4449 outputs 11-bit data on the Dxx13P, Dxx13M and Dxx3P, Dxx3M pins and

OVR information on the Dxx0P, Dxx0M pins. When the ALWAYS WRITE 1 bits are set, the ADC outputs 13-bit

data on the Dxx13P, Dxx13M and Dxx1P, Dxx1M pins and OVR information on the Dxx0P, Dxx0M pins. To

enable 14-bit resolution, the DIS OVR ON LSB register bit must be set to '1' as indicated in Table 6.

Table 6. ADC configuration

DATA ON ADC PINS

ALWAYS WRITE 1 = 1

ADC PIN NAMES

AFTER RESET

ALWAYS WRITE 1 = 1

DIS OVR ON LSB = 1

Dxx13

D13

—

Dxx3

Dxx2

Logic 0

Dxx1

Logic 1

Dxx0

OVR

11-bit data (D[13:3]) and OVR come

13-bit data (D[13:1]) and OVR come

14-bit data comes on ADC output

Comments

on ADC output pins

pins

ANALOG INPUT

The analog input consists of a switched-capacitor-based differential sample-and-hold architecture. This

differential topology results in very good ac performance even for high input frequencies at high sampling rates.

The INP and INM pins must be externally biased around a common-mode voltage of 1.15 V, available on the

VCM pin. For a full-scale differential input, each input pin (INP, INM) must swing symmetrically between VCM +

0.5 V and VCM – 0.5 V, resulting in a 2-VPP differential input swing.

The input sampling circuit has a high 3-dB bandwidth that extends up to 500 MHz when a 50-

Ω source drives the

ADC analog inputs.

Drive Circuit Requirements

For optimum performance, the analog inputs must be driven differentially. This configuration improves the

common-mode noise immunity and even-order harmonic rejection. A 5-

Ω to 15-Ω resistor in series with each

input pin is recommended to damp out ringing caused by package parasitics.

Spurious-free dynamic range (SFDR) performance can be limited because of several reasons (such as the effect

of sampling glitches, sampling circuit nonlinearity, and quantizer nonlinearity that follows the sampling circuit).

Depending on the input frequency, sampling rate, and input amplitude, one of these metrics plays a dominant

part in limiting performance. At very high input frequencies, SFDR is determined largely by the device sampling

circuit nonlinearity. At low input amplitudes, the quantizer nonlinearity typically limits performance.

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