ADS4449 datasheet(45/54 Pages) TI

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CLKP

5 kΩ

0.95V

5 kΩ

20 Ω

LPKG

~ 2 nH

CBOND

~ 1 pF

LPKG

~ 2 nH

RESR

~ 100 Ω

RESR

~ 100 Ω

CLKM

Clock Buffer

CEQ

CBOND

~ 1 pF

ADS4449

www.ti.com

SBAS603 – APRIL 2013

Input Common Mode

To ensure a low-noise, common-mode reference, the VCM pin should be filtered with a 0.1-µF, low-inductance

capacitor connected to ground. The VCM pin is designed to directly bias the ADC inputs (refer to Figure 48 to

Figure 51).

Each ADC input pin sinks a common-mode current of approximately 1.5 µA per MSPS of clock frequency. When

a differential amplifier is used to drive the ADC (with dc-coupling), ensure that the output common-mode of the

amplifier is within the acceptable input common-mode range of the ADC inputs (VCM ± 25 mV).

Clock Input

The ADS4449 clock inputs can be driven differentially with a sine, LVPECL, or LVDS source with little or no

difference in performance between them. The common-mode voltage of the clock inputs is set to 0.95 V using

internal 5-k

Ω resistors, as shown in Figure 55. This setting allows the use of transformer-coupled drive circuits for

sine-wave clock or ac-coupling for LVPECL, LVDS, and LVCMOS clock sources (see Figure 56, Figure 57, and

Figure 58).

For best performance, the clock inputs must be driven differentially, thereby reducing susceptibility to common-

mode noise. TI recommends keeping the differential voltage between clock inputs less than 1.8 VPP to obtain

best performance. A clock source with very low jitter is recommended for high input frequency sampling. Band-

pass filtering of the clock source can help reduce the effects of jitter. With a non-50% duty cycle clock input,

performance does not change.

NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.

Figure 55. Internal Clock Buffer

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