ADS4449 datasheet(8/54 Pages) TI

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Ch B

(Ch D)

Input

Clock

CLKOUTABM

(CLKOUTCDM)

CLKOUTABP

(CLKOUTCDP)

Output Data

DABP, DABM

(DCDP, DCDM)

DDR

LVDS

Input

Signal

Sample

N+1

N+2

N+3

N+4

CLKINM

CLKINP

N+10

N+11

N+12

N-1

N+1

N-10

N-9

N-8

N-7

tPDI

Ch A

(Ch C)

Ch B

(Ch D)

Ch A

(Ch C)

Ch B

(Ch D)

Ch A

(Ch C)

Ch B

(Ch D)

Ch A

(Ch C)

Ch B

(Ch D)

Ch A

(Ch C)

Ch A

(Ch C)

Ch B

(Ch D)

Ch A

(Ch C)

Ch B

(Ch D)

Ch A

(Ch C)

Ch B

(Ch D)

Ch A

(Ch C)

Ch B

(Ch D)

Ch A

(Ch C)

10 Clock Cycles

DxnP

DxnM

GND

Logic 0

ODL

Logic 1

ODH

OCM

ADS4449

SBAS603 – APRIL 2013

www.ti.com

PARAMETRIC MEASUREMENT INFORMATION

LVDS OUTPUT TIMING

Figure 3 shows a timing diagram of the LVDS output voltage levels. Figure 4 shows the latency described in the

Timing Requirements table.

Figure 3. LVDS Output Voltage Levels

Figure 4. Latency Timing

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