ADS4449 datasheet(6/54 Pages) TI

6 / 54 page

ADS4449

SBAS603 – APRIL 2013

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC clock frequency = 250 MHz,

50% clock duty cycle, AVDD33V = 3.3 V, AVDD = 1.9 V, DRVDD = 1.8 V, and –1-dBFS differential input, unless otherwise

noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

DYNAMIC AC CHARACTERISTICS (continued)

fIN = 40 MHz

100

dBc

fIN = 70 MHz

100

dBc

fIN = 140 MHz

dBc

Worst spur

fIN = 170 MHz

dBc

(non HD2, HD3)

fIN = 220 MHz,

dBc

fIN = 307 MHz

dBc

fIN = 350 MHz

dBc

DNL

Differential nonlinearity

-0.95

±0.5

LSBs

INL

Integral nonlinearity

±1.5

±5.25

LSBs

Recovery to within 1% (of final value) for

Clock

Input overload recovery

6-dB output overload with sine-wave input

cycle

With a full-scale, 220-MHz signal on

Crosstalk

aggressor channel and no signal on victim

channel

PSRR

AC power-supply rejection ratio

For 50-mVPP signal on AVDD supply

< 30

DIGITAL CHARACTERISTICS

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level '0' or '1'. AVDD33 = 3.3 V, AVDD = 1.9 V, and DRVDD = 1.8 V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS(1) (RESET, SCLK, SDATA, SEN, PDN)

All digital inputs support 1.8-V logic

VIH

High-level input voltage

1.25

levels. SPI supports 3.3-V logic levels.

All digital inputs support 1.8-V logic

VIL

Low-level input voltage

0.45

levels. SPI supports 3.3-V logic levels.

RESET, SCLK, PDN pins

VHIGH = 1.8 V

µA

High-level input

IIH

current

SEN(2) pin

VHIGH = 1.8 V

µA

RESET, SCLK, PDN pins

VLOW = 0 V

µA

Low-level input

IIL

current

SEN pin

VLOW = 0 V

µA

DIGITAL OUTPUTS (SDOUT)

DRVDD –

VOH

High-level output voltage

DRVDD

0.1

VOL

Low-level output voltage

0.1

DIGITAL OUTPUTS, LVDS INTERFACE

(DAB[13:0]P, DAB[13:0]M, DCD[13:0]P, DCD[13:0]M, CLKOUTABP, CLKOUTABM, CLKOUTCDP, CLKOUTCDM)

VODH

High(3)

Standard-swing LVDS

270

350

465

Output differential

voltage

VODL

Low

Standard-swing LVDS

–465

–350

–270

VOCM

Output common-mode voltage

1.05

(1)

RESET, SDATA, and SCLK have an internal 150-k

Ω pull-down resistor.

(2)

SEN has an internal 150-k

Ω pull-up resistor to DRVDD.

(3)

With an external 100-

Ω termination.

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