ADS4449 datasheet(7/54 Pages) TI

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ADS4449

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SBAS603 – APRIL 2013

TIMING REQUIREMENTS

(1)

Typical values are at +25°C, AVDD33 = 3.3 V, AVDD = 1.9 V, DRVDD = 1.8 V, sine-wave input clock, CLOAD = 3.3 pF

(2), and

RLOAD = 100 Ω

(3), unless otherwise noted.

Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Aperture delay

0.7

1.2

1.6

Aperture delay matching

Between any two channels of the same device

±70

Between two devices at the same temperature and

Variation of aperture delay

±150

DRVDD supply

Aperture jitter

140

fs rms

Time to valid data after coming out of global power

100

µs

down

Wake up time

Time to valid data after coming out of channel power

µs

down

Output clock

Default latency in 14-bit mode

cycles

Output clock

ADC latency(4)(5)

Digital gain enabled

cycles

Output clock

Digital gain and offset correction enabled

cycles

OUTPUT TIMING(6)

tSU

Data setup time(7)(8)(9)

Data valid to CLKOUTxxP zero-crossing

0.6

0.85

Data hold time(7)(8)(9)

CLKOUTxxP zero-crossing to data becoming invalid

0.6

0.84

Differential clock duty cycle (CLKOUTxxP –

LVDS bit clock duty cycle

50%

CLKOUTxxM)

Input clock falling edge cross-over to output clock

tPDI

Clock propagation delay(5)

falling edge cross-over, 184 MSPS

≤ sampling

0.25 × tS + tdelay

frequency

≤ 250 MSPS

Input clock falling edge cross-over to output clock

tdelay

Delay time

falling edge cross-over, 184 MSPS

≤ sampling

6.9

8.65

10.5

frequency

≤ 250 MSPS

tRISE,

Data rise and fall time

Rise time measured from –100 mV to +100 mV

0.1

tFALL

tCLKRISE,

Output clock rise and fall

Rise time measured from –100 mV to +100 mV

0.1

tCLKFALL

time

(1)

Timing parameters are ensured by design and characterization and are not tested in production.

(2)

CLOAD is the effective external single-ended load capacitance between each output pin and ground.

(3)

RLOAD is the differential load resistance between the LVDS output pair.

(4)

ADC latency is given for channels B and D. For channels A and C, latency reduces by half of the output clock cycles.

(5)

Overall latency = ADC latency + tPDI.

(6)

Measurements are done with a transmission line of 100-

Ω characteristic impedance between the device and load. Setup and hold time

specifications take into account the effect of jitter on the output data and clock.

(7)

Data valid refers to a logic high of +100 mV and a logic low of –100 mV.

(8)

Note that these numbers are taken with delayed output clocks by writing the following registers: address A9h, value 02h; and address

ACh, value 60h. Refer to the Serial Interface Registers section. By default after reset, minimum setup time and minimum hold times are

520 ps each.

(9)

The setup and hold times of a channel are measured with respect to the same channel output clock.

Table 2. LVDS Timings Across Lower Sampling Frequencies

SETUP TIME (ns)

HOLD TIME (ns)

SAMPLING FREQUENCY

(MSPS)

MIN

TYP

MAX

MIN

TYP

MAX

210

0.89

1.03

0.82

1.01

185

1.06

1.21

0.95

1.15

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