AM79C976 datasheet(225/309 Pages) AMD

225 / 309 page

8/01/00

Am79C976

225

P R E L I M INARY

7-0

PMR_B3

Pattern Match RAM Byte 3. This

byte is written into or read from

Byte 3 of Pattern Match RAM.

Read

and

write

accessible.

PMR_B3

undefined

after

H_RESET, and is unaffected by

S_RESET and the STOP bit.

Initialization Block

Note: When SSIZE32 (BCR20, bit 8) is set to 0, the

software structures are defined to be 16 bits wide. The

base address of the initialization block must be aligned

to a word boundary, i.e., CSR1, bit 0 must be cleared to

0. When SSIZE32 is set to 0, the initialization block

looks like Table 96.

Note: The Am79C976 controller performs DWord ac-

cesses to read the initialization block. This statement is

always true, regardless of the setting of the SSIZE32

bit.

When SSIZE32 (BCR20, bit 8) is set to 1, the software

structures are defined to be 32 bits wide. The base ad-

dress of the initialization block must be aligned to a

DWord boundary, i.e., CSR1, bits 1 and 0 must be

cleared to 0. When SSIZE32 is set to 1, the initialization

block looks like Table 97.

5/(1 DQG7/(1

When SSIZE32 (BCR20, bit 8) is set to 0, the software

structures are defined to be 16 bits wide, and the RLEN

and TLEN fields in the initialization block are each three

bits wide. The values in these fields determine the num-

ber of transmit and receive Descriptor Ring Entries

(DRE) which are used in the descriptor rings. Their

meaning is shown in Table 98. If a value other than those

listed in Table 98 is desired, CSR76 and CSR78 can be

written after initialization is complete.

When SSIZE32 (BCR20, bit 8) is set to 1, the software

structures are defined to be 32 bits wide, and the RLEN

Table 96. Initialization Block (SSIZE32 = 0)

Address

Bits 15-13

Bit 12

Bits 11-8

Bits 7-4

Bits 3-0

IADR+00h

MODE 15-00

IADR+02h

PADR 15-00

IADR+04h

PADR 31-16

IADR+06h

PADR 47-32

IADR+08h

LADRF 15-00

IADR+0Ah

LADRF 31-16

IADR+0Ch

LADRF 47-32

IADR+0Eh

LADRF 63-48

IADR+10h

RDRA 15-00

IADR+12h

RLEN

RES

RDRA 23-16

IADR+14h

TDRA 15-00

IADR+16h

TLEN

RES

TDRA 23-16

Table 97. Initialization Block (SSIZE32 = 1)

Address

Bits

31-28

27-24

23-20

19-16

15-12

11-8

7-4

3-0

IADR+00h

TLEN

RES

RLEN

RES

MODE

IADR+04h

PADR 31-00

IADR+08h

RES

PADR 47-32

IADR+0Ch

LADRF 31-00

IADR+10h

LADRF 63-32

IADR+14h

RDRA 31-00

IADR+18h

TDRA 31-00

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