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AM79C976 Datasheet(PDF) 223 Page - Advanced Micro Devices |
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AM79C976 Datasheet(HTML) 223 Page - Advanced Micro Devices |
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223 / 309 page  8/01/00 Am79C976 223 P R E L I M INARY S_RESET or setting the STOP bit. %&5 3&, '$7$ 5HJLVWHU6L[ '$7$ $OLDV 5HJLVWHU Note: This register is an alias of the DATA register and also of the DATA_SCALE field of the PCMCR register. Since these two are read only, BCR43 provides a means of programming them through the EEPROM. The contents of this register are copied into the corre- sponding fields pointed with the DATA_SEL field set to six. Bits 15-0 in this register are programmable through the EEPROM. Bit Name Description 15-10 RES Reserved locations. Written as zeros and read as undefined. 9-8 D6_SCALE These bits correspond to the DATA_SCALE field of the PMC- SR (offset Register 44 of the PCI configuration space, bits 14-13). Refer to the description of DATA_SCALE for the meaning of this field. D6_SCALE is read only. Cleared by H_RESET and is not affected by S_RESET or setting the STOP bit 7-0 DATA6 These bits correspond to the PCI DATA register (offset Register 47 of the PCI configuration space, bits 7-0). Refer to the description of DATA register for the meaning of this field. DATA6 is read only. Cleared by H_RESET and is not affected by S_RESET or setting the STOP bit. %&5 3&, '$7$ 5HJLVWHU6HYHQ '$7$ $OLDV 5HJLVWHU Note: This register is an alias of the DATA register and also of the DATA_SCALE field of the PCMCR register. Since these two are read only, BCR44 provides a means of programming them through the EEPROM. The contents of this register are copied into the corre- sponding fields pointed with the DATA_SEL field set to seven. Bits 15-0 in this register are programmable through the EEPROM. Bit Name Description 15-10 RES Reserved locations. Written as zeros and read as undefined. 9-8 D7_SCALE These bits correspond to the DATA_SCALE field of the PMC- SR (offset Register 44 of the PCI configuration space, bits 14-13). Refer to the description of DATA_SCALE for the meaning of this field. D7_SCALE is read only. Cleared by H_RESET and is not affected by S_RESET or setting the STOP bit. 7-0 DATA7 These bits correspond to the PCI DATA register (offset register 47 of the PCI configuration space, bits 7-0). Refer to the description of DATA register for the meaning of this field. DATA7 is read only. Cleared by H_RESET and is not affected by S_RESET or setting the STOP bit. %&5 2Q1RZ 3DWWHUQ 0DWFKLQJ5HJLVWHU Note: This register is used to control and indirectly ac- cess the Pattern Match RAM (PMR). When BCR45 is written and the PMAT_MODE bit (bit 7) is 1, Pattern Match logic is enabled. No bus accesses into PMR are possible, and BCR46, BCR47, and all other bits in BCR45 are ignored. When PMAT_MODE is set, a read of BCR45, BCR46, or BCR47 returns all undefined bits except for PMAT_MODE. When BCR45 is written and the PMAT_MODE bit is 0, the Pattern Match logic is disabled and accesses to the PMR are possible. Bits 6-0 of BCR45 specify the ad- dress of the PMR word to be accessed. Following the write to BCR45, the PMR word may be read by reading BCR45, BCR46 and BCR47 in any order. To write to PMR word, the write to BCR45 must be followed by a write to BCR46 and a write to BCR47 in that order to complete the operation. The RAM will not actually be written until the write to BCR47 is complete. The write to BCR47 causes all 5 bytes (four bytes of BCR46-47 and the upper byte of the BCR45) to be written to what- ever PMR word is addressed by bits 6:0 of BCR45. Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-8 PMR_B0 Pattern Match RAM Byte 0. This byte is written into or read from Byte 0 of the Pattern Match RAM. Read and write accessible. PMR_B0 is undefined after |
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