AM79C976 datasheet(219/309 Pages) AMD

219 / 309 page

8/01/00

Am79C976

219

P R E L I M INARY

external PHY. This bit is needed

when there is no way to guaran-

tee the state of the external PHY.

This bit must be reprogrammed

after every H_RESET.

Read/Write

accessible.

XPH-

YRST is set to 0 by H_RESET

and is unaffected by S_RESET

and the STOP bit. XPHYRST is

only valid when the internal Net-

work Port Manager is scanning

for a network port.

XPHYANE

External PHY Auto-Negotiation

Enable. This bit will force the ex-

ternal PHY into enabling Auto-

Negotiation. When set to 0 the

Am79C976 controller will send a

MII management frame disabling

Auto-Negotiation.

Read/Write

accessible.

XPHYANE

set

H_RESET and is unaffected by

S_RESET and the STOP bit.

XPHYANE is only valid when the

internal Network Port Manager is

scanning for a network port.

XPHYFD

External PHY Full Duplex. When

set, this bit will force the external

PHY into full duplex when Auto-

Negotiation is not enabled.

Read/Write accessible. XPHYFD

is set to 0 by H_RESET, and is

unaffected by S_RESET and the

STOP bit. XPHYFD is only valid

when the internal Network Port

Manager is scanning for a net-

work port.

XPHYSP

External PHY Speed. When set,

this bit will force the external PHY

into 100 Mbps mode when Auto-

Negotiation is not enabled.

Read/Write accessible. XPHYSP

is set to 0 by H_RESET, and is

unaffected by S_RESET and the

STOP bit. XPHYSP is only valid

when the internal Network Port

Manager is scanning for a net-

work port.

RES

Reserved location. Written as ze-

ros and read as undefined.

MIIILP

Media Independent Interface In-

ternal Loopback. When set, this

bit will cause the internal portion

of the MII data port to loop back

on itself. The interface is mapped

the

following

way.

The

TXD[3:0] nibble data path is

looped back onto the RXD[3:0]

nibble data path. TX_CLK is

looped back as RX_CLK. TX_EN

is looped back as RX_DV. CRS is

correctly OR’d with TX_EN and

RX_DV and always encompass-

es the transmit frame. TX_ER is

looped back as RX_ER. Howev-

er, TX_ER will not get asserted

by the Am79C976 controller to

signal an error. The TX_ER func-

tion is reserved for future use.

Read/Write accessible. MIIILP is

set to 0 by H_RESET and is unaf-

fected by S_RESET and the

STOP bit.

RES

Reserved location. Written as ze-

ros and read as undefined.

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Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-10

RES

Reserved locations. Written as

zeros and read as undefined.

9-5

PHYAD

MII Management Frame PHY Ad-

dress. PHYAD contains the 5-bit

PHY Address field that is used in

the management frame that gets

clocked out via the MII manage-

ment port pins (MDC and MDIO)

whenever a read or write transac-

tion occurs to BCR34. The PHY

address 1Fh is not valid.

Read/Write accessible. PHYAD

is undefined after H_RESET and

is unaffected by S_RESET and

the STOP bit.

The PHYAD field is loaded from

bits [9:5] of the AUTOPOLL0 reg-

ister when AUTOPOLL0 is load-

ed from EEPROM.

4-0

REGAD

MII Management Frame Register

Address. REGAD contains the

AM79C976 Datasheet(PDF) 219 Page - Advanced Micro Devices

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