AM79C976 datasheet(216/309 Pages) AMD

216 / 309 page

216

Am79C976

8/01/00

P R E L I M INARY

Values larger than IFFCh will

cause incorrect behavior.

Note:

The

minimum

allowed

number of pages is four and the

maximum is SRAM_SIZE-4. The

Am79C976 controller will not op-

erate correctly with less than four

pages of memory per queue. See

Table 93 for SRAM_BND pro-

gramming details.

CAUTION:

Programming

SRAM_BND and SRAM_SIZE to

the same value will cause data

corruption.

Read/Write

accessible.

SRAM_BND is set to 00000000b

during H_RESET and is unaffect-

ed by S_RESET or STOP.

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Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

PTR TST

Reserved. Reserved for manu-

facturing tests. Written as zero

and read as undefined.

Note: Use of this bit will cause

data corruption and erroneous

operation.

Read/Write

accessible.

PTR_TST

set

H_RESET and is unaffected by

S_RESET and the STOP bit.

LOLATRX

Obsolete function. Writing has no

effect. Read as undefined.

13-6

RES

Reserved locations. Written as

zeros and read as undefined.

5-3

EBCS

Obsolete function. Writing has no

effect. Read as undefined.

2-0

CLK_FAC

Obsolete function. Writing has no

effect. Read as undefined.

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Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

EPADDRL

Expansion Port Address Lower.

This address is used to provide

addresses for the Flash port ac-

cesses.

Flash accesses are started when

a read or write is performed on

BCR30. During Flash accesses

all bits in EPADDR are valid.

Read accessible always; write

accessible only when

STOP is

set

when

SRAM_SIZE

(BCR25, bits 7-0) is 0. EPADDRL

is undefined after H_RESET and

is unaffected by S_RESET or

STOP.

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Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

FLASH

Obsolete function. Read only. Al-

ways returns logic 1.

LAAINC

Lower Address Auto Increment.

When the LAAINC bit is set to 1,

the Expansion Port Lower Ad-

dress will automatically increment

by one after a read or write ac-

cess to EBDATA (BCR30). When

EBADDRL reaches FFFFh and

LAAINC is set to 1, the Expansion

Port Lower Address (EPADDRL)

will roll over to 0000h. When the

LAAINC bit is set to 0, the Expan-

sion Port Lower Address will not

be affected in any way after an

access to EBDATA (BCR30) and

must be programmed.

Read accessible always; write

accessible only when the STOP

bit is set. LAINC is 0 after

H_RESET and is unaffected by

S_RESET or the STOP bit.

Table 93. SRAM_BND Programming

SRAM Addresses

SRAM_BND 11:0]

Minimum SRAM_BND

Address

004h

Maximum SRAM_BND Address

SRAM_SIZE - 4

AM79C976 Datasheet(PDF) 216 Page - Advanced Micro Devices

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