AM79C976 datasheet(213/309 Pages) AMD

213 / 309 page

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Am79C976

213

P R E L I M INARY

The value of the SSIZE32 bit has

no effect on the drive of the upper

8 address bits. The upper 8 ad-

dress pins are always driven, re-

gardless of the state of the

SSIZE32 bit.

Note that the setting of the

SSIZE32 bit has no effect on the

defined width for I/O resources.

I/O resource width is determined

by the state of the DWIO bit

(BCR18, bit 7).

7-0

SWSTYLE

Software Style register. The val-

ue in this register determines the

style of register and memory re-

sources that shall be used by the

Am79C976 controller. The Soft-

ware Style selection will affect the

interpretation of a few bits within

the CSR space, the order of the

descriptor entries and the width

of the descriptors and initializa-

tion block entries.

All Am79C976 controller CSR

bits and all descriptor, buffer, and

initialization block entries not cit-

ed in the Table 92 are unaffected

by the Software Style selection

and are, therefore, always fully

functional as specified in the CSR

and BCR sections.

Read/Write accessible. The SW-

STYLE register will contain the

value 00h following H_RESET

and

will

unaffected

S_RESET or STOP.

AM79C976 Datasheet(PDF) 213 Page - Advanced Micro Devices

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