AM79C976 datasheet(209/309 Pages) AMD

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8/01/00

Am79C976

209

P R E L I M INARY

cleared, this bit indicates that the

Am79C976

controller

pro-

grammed for Word I/O (WIO)

mode. This bit affects the I/O Re-

source Offset map and it affects

the

defined

width

the

Am79C976 controllers I/O re-

sources. See the DWIO and WIO

sections for more details.

The initial value of the DWIO bit is

determined by the programming

of the EEPROM.

The value of DWIO can be al-

tered

automatically

the

Am79C976 controller. Specifical-

ly, the Am79C976 controller will

set DWIO if it detects a DWord

write access to offset 10h from

the

Am79C976

controller

I/O

base address (corresponding to

the RDP resource).

Once the DWIO bit has been set

to a 1, only a H_RESET or an EE-

PROM read can reset it to a 0.

(Note that the EEPROM read op-

eration will only set DWIO to a 0 if

the appropriate bit inside of the

EEPROM is set to 0.)

DWIO is read only, write opera-

tions have no effect. DWIO is

cleared by H_RESET and is not

affected S_RESET or by setting

the STOP bit.

BREADE

Obsolete function. Writing has no

effect. Read as undefined.

BWRITE

Obsolete function. Writing has no

effect. Read as undefined.

4-3

TSTSHDW Reserved locations. Written and

read as zeros.

2-0

LINBC

Reserved locations. Written and

read as zeros.

%&5((3520 &RQWURODQG6WDWXV

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

PVALID

EEPROM

Valid

status

bit.

PVALID is read only; write opera-

tions have no effect. A value of 1

in this bit indicates that a PREAD

operation has occurred, and that

(1) there is an EEPROM connect-

ed to the Am79C976 controller in-

terface pins and (2) the contents

read from the EEPROM have

passed the checksum verification

operation.

A value of 0 in this bit indicates a

failure in reading the EEPROM.

The checksum for the EEPROM

contents is incorrect or no EE-

PROM is connected to the inter-

face pins.

PVALID

set

during

H_RESET and is unaffected by

S_RESET or the STOP bit. How-

ever, following the H_RESET op-

eration, an automatic, sequential

read of the EEPROM will be per-

formed. Just as is true for the nor-

mal PREAD command, at the

end of this automatic, sequential

read operation, the PVALID bit

may be set to 1. Therefore,

H_RESET will set the PVALID bit

to 0 at first, but the automatic EE-

PROM read operation may later

set PVALID to a 1.

If PVALID becomes 0 following

an EEPROM read operation (ei-

ther automatically generated af-

ter

H_RESET,

requested

through PREAD), then all EE-

PROM-programmable BCR loca-

tions

will

reset

their

H_RESET values. The content of

the Address PROM locations,

however, will not be cleared.

If no EEPROM is present at the

EESK, EEDI, and EEDO pins,

then all attempted PREAD com-

mands will terminate early and

PVALID will not be set. This ap-

plies to the automatic read of the

EEPROM after H_RESET, as

well as to host-initiated PREAD

commands.

PREAD

EEPROM Read command bit.

When this bit is set to a 1 by the

host, the PVALID bit (BCR19, bit

15) will immediately be reset to a

0, and then the Am79C976 con-

troller will perform a sequential

AM79C976 Datasheet(PDF) 209 Page - Advanced Micro Devices

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