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AM79C976 Datasheet(PDF) 208 Page - Advanced Micro Devices |
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AM79C976 Datasheet(HTML) 208 Page - Advanced Micro Devices |
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208 / 309 page  208 Am79C976 8/01/00 P R E L I M INARY %&5 ,2 %DVH $GGUHVV 8SSHU Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 IOBASEU Reserved locations. After H_RESET, the value in this regis- ter will be undefined. The settings of this register will have no effect on any Am79C976 controller function. It is only included for software compatibility with other PCnet family devices. Read/Write accessible. IO- BASEU is not affected by S_RESET or STOP. %&5 %XUVWDQG %XV&RQWURO5HJLVWHU Note: Bits 15-0 in this register are programmable through the EEPROM. Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-12 ROMTMG Expansion ROM Timing. The val- ue of ROMTMG is used to tune the timing for all accesses to the external Flash/EPROM. ROMTMG defines the amount of time that a valid address is driven on the ERA[19:0] pins. The register value specifies delay in number of ROMCLK cycles, where ROMCLK is an internal clock signal that runs at one fourth the speed of ERCLK. Note: Programming ROMTNG with a value of 0 is not permitted. To ensure adequate expansion ROM setup time, ROMTMG should be set to 1 plus tACC / (ROMCLK period), where tACC is the access time of the expan- sion ROM device (Flash or EPROM). (The extra ROMCLK cycle is added to account for the ERA[19:0] output delay from ROMCLK plus the ERD[7:0] set- up time to ROMCLK.) This field is an alias of CTRL0, bits 11-8. Read/Write accessible. ROMT- MG is set to the value of 1001b by H_RESET and is not affected by S_RESET or STOP. The default value allows the use of an Expan- sion ROM with an access time of 350 ns if ERCLK is running at 90 MHz. 11 NOUFLO No Underflow on Transmit. When the NOUFLO bit is set to 1, the Am79C976 controller will not start transmitting the preamble for a packet until the Transmit Start Point (CTRL1, bits 16-17) requirement has been met and the complete packet has been copied into the transmit FIFO. When the NOUFLO bit is cleared to 0, the Transmit Start Point is the only restriction on when pre- amble transmission begins for transmit packets. Setting the NOUFLO bit guaran- tees that the Am79C976 control- ler will never suffer transmit underflows, because the arbiter that controls transfers to and from the SSRAM guarantees a worst case latency on transfers to and from the MAC and Bus Transmit FIFOs such that it will never un- derflow if the complete packet has been copied into the Am79C976 controller before packet transmission begins. Read/Write accessible. NOUFLO is cleared to 0 after H_RESET or S_RESET and is unaffected by STOP. 10 RES Reserved location. Written as ze- ros and read as undefined. 9 MEMCMD Obsolete function. Writing has no effect. Read as undefined. 8 EXTREQ Obsolete function. Writing has no effect. Read as undefined. 7 DWIO Double Word I/O. When set, this bit indicates that the Am79C976 controller is programmed for DWord I/O (DWIO) mode. When |
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