AM79C976 datasheet(217/309 Pages) AMD

217 / 309 page

8/01/00

Am79C976

217

P R E L I M INARY

13-8

RES

Reserved locations. Written as

zeros and read as undefined.

7-0

EPADDRU

Expansion Port Address Upper.

This upper portion of the Expan-

sion Bus address is used to pro-

vide addresses for Flash/EPROM

port accesses.

Read accessible always; write

accessible only when the STOP

bit is set or when SRAM SIZE

(BCR25, bits 7-0) is 0. EPADD-

RU is undefined after H_RESET

and is unaffected by S_RESET or

the STOP bit.

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Bit

Name

Description

31-8

RES

Reserved locations. Written as

zeros and read as undefined.

7-0

EBDATA

Expansion Bus Data Port. EBDA-

TA is the data port for operations

on the Expansion Port involving

Flash accesses.

Flash read cycles are performed

when BCR30 is read. Upon com-

pletion of the read cycle, the 8-bit

result for Flash access is stored

in EBDATA[7:0]. Flash write cy-

cles are performed when BCR30

is written and the FLASH bit

(BCR29, bit 15) is set to 1.

Read and write accessible. EB-

DATA

undefined

after

H_RESET, and is unaffected by

S_RESET and the STOP bit.

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Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

STVAL

Software Timer Value. STVAL

controls the maximum time for

the Software Timer to count be-

fore

generating

the

STINT

(CSR7, bit 11) interrupt. The Soft-

ware Timer is a free-running tim-

er that is started upon the first

write to STVAL. After the first

write, the Software Timer will

continually count and set the

STINT interrupt at the STVAL pe-

riod.

The STVAL value is interpreted

as an unsigned number with a

resolution of 10.24µs. For in-

stance, if STVAL is set to 48,828

(0BEBCh), the Software Timer

period will be 0.5 s.

Setting STVAL to a value of 0 will

result in erratic behavior.

Read

and

write

accessible.

STVAL is set to FFFFh after

H_RESET and is unaffected by

S_RESET and the STOP bit.

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Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

ANTST

Reserved

for

manufacturing

tests. Written as 0 and read as

undefined.

Note: Use of this bit will cause

data corruption and erroneous

operation.

Read/Write accessible. ANTST is

set to 0 by H_RESET and is unaf-

fected by S_RESET and the

STOP bit.

MIIPD

MII PHY Detect. MIIPD reflects

the quiescent state of the MDIO

pin. MIIPD is continuously updat-

ed whenever there is no manage-

ment operation in progress on the

MII interface. When a manage-

ment operation begins on the in-

terface, the state of MIIPD is

preserved

until

the

operation

ends, when the quiescent state is

again monitored and continuous-

ly updates the MIIPD bit. When

the MDIO pin is at a quiescent

LOW state, MIIPD is cleared to 0.

When the MDIO pin is at a quies-

cent HIGH state, MIIPD is set to

1. Any transition on the MIIPD bit

will set the MIIPDTINT bit (CSR7,

bit 1).

AM79C976 Datasheet(PDF) 217 Page - Advanced Micro Devices

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