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AM79C976 Datasheet(PDF) 229 Page - Advanced Micro Devices |
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AM79C976 Datasheet(HTML) 229 Page - Advanced Micro Devices |
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229 / 309 page  8/01/00 Am79C976 229 P R E L I M INARY The following tables describe the bits of the receive descriptors in more detail. 7DEOH 5HFHLYH'HVFULSWRU 6:67</( Offset Bit Name Description 0 15-0 RBADR Receive Buffer Address. This field contains the address of the receive buffer that is associated with this descriptor. 2 15 OWN This bit indicates whether the descriptor entry is owned by the host (OWN = 0) or by the Am79C976 controller (OWN = 1). The host sets the OWN bit after it has emptied the buffer pointed to by the descriptor entry. The Am79C976 controller clears the OWN bit after filling the buffer that the description points to. Both the Am79C976 controller and the host must not alter a descriptor entry after it has relinquished ownership. 14 ERR Error Summary. ERR is the OR of FRAM, OFLO, and CRC. ERR is set by the Am79C976 controller and cleared by the host. 13 FRAM Framing error indicates that the incoming frame contains a non-integer multiple of eight bits and there was an FCS error. If there was no FCS error on the incoming frame, then FRAM will not be set even if there was a non- integer multiple of eight bits in the frame. FRAM is not valid in internal loopback mode. FRAM is valid only when ENP is set and OFLO is not. FRAM is set by the Am79C976 controller and cleared by the host. 12 OFLO Overflow error indicates that the receiver has lost all or part of the incoming frame, due to an inability to move data from the receive FIFO into a memory buffer before the internal FIFO overflowed. OFLO is set by the Am79C976 controller and cleared by the host. 11 CRC CRC indicates that the receiver has detected a CRC (FCS) error on the incoming frame. CRC is valid only when ENP is set and OFLO is not. CRC is set by the Am79C976 controller and cleared by the host. CRC will also be set when Am79C976 receives an RX_ER indication from the external PHY through the MII. 10 Reserved. 9STP Start of Packet indicates that this is the first buffer used by the Am79C976 controller for this frame. If STP and ENP are both set to 1, the frame fits into a single buffer. Otherwise, the frame is spread over more than one buffer. When LAPPEN (CSR3, bit 5) is cleared to 0, STP is set by the Am79C976 controller and cleared by the host. When LAPPEN is set to 1, STP must be set by the host. 8ENP End of Packet indicates that this is the last buffer used by the Am79C976 controller for this frame. It is used for data chaining buffers. If both STP and ENP are set, the frame fits into one buffer and there is no data chaining. ENP is set by the Am79C976 controller and cleared by the host. 7-0 RBADR[23:16] Receive Buffer Address (high order bits) 4 15-0 BCNT Buffer Byte Count is the length of the buffer pointed to by this descriptor, expressed as the two’s complement of the length of the buffer. This field is written by the host and unchanged by the Am79C976 controller. 6 15-12 ZEROS This field is reserved. Am79C976 controller will write zeros to these locations. 11-0 MCNT Message Byte Count is the number of bytes of the received message written to the receive buffer. This is the actual frame length (including FCS) unless stripping is enabled and the length field is < 46 bytes. In this case, MCNT is 14 + length_field. MCNT can take values in the range 15 to 59 and values greater than or equal to 64. MCNT is expressed as an unsigned binary integer. MCNT is valid only when ERR is clear and ENP is set. MCNT is written by the Am79C976 controller and cleared by the host. |
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