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AM79C976 Datasheet(PDF) 230 Page - Advanced Micro Devices |
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AM79C976 Datasheet(HTML) 230 Page - Advanced Micro Devices |
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230 / 309 page  230 Am79C976 8/01/00 P R E L I M INARY 7DEOH 5HFHLYH'HVFULSWRU 6:67</( Offset Bit Name Description 0 31-0 RBADR[31:0] Receive Buffer Address. This field contains the address of the receive buffer that is associated with this descriptor. 431 OWN This bit indicates whether the descriptor entry is owned by the host (OWN = 0) or by the Am79C976 controller (OWN = 1). The host sets the OWN bit after it has emptied the buffer pointed to by the descriptor entry. The Am79C976 controller clears the OWN bit after filling the buffer that the descriptor points to. Both the Am79C976 controller and the host must not alter a descriptor entry after it has relinquished ownership. 430 ERR Error Summary. ERR is the OR of FRAM, OFLO, and CRC. ERR is set by the Am79C976 controller and cleared by the host. 429 FRAM Framing error indicates that the incoming frame contains a non-integer multiple of eight bits and there was an FCS error. If there was no FCS error on the incoming frame, then FRAM will not be set even if there was a non-integer multiple of eight bits in the frame. FRAM is not valid in internal loopback mode. FRAM is valid only when ENP is set and OFLO is not. FRAM is set by the Am79C976 controller and cleared by the host. 428 OFLO Overflow error indicates that the receiver has lost all or part of the incoming frame, due to an inability to move data from the receive FIFO into a memory buffer before the internal FIFO overflowed. OFLO is set by the Am79C976 controller and cleared by the host. 4 27 CRC CRC indicates that the receiver has detected a CRC (FCS) error on the incoming frame. CRC is valid only when ENP is set and OFLO is not. CRC is set by the Am79C976 controller and cleared by the host. CRC will also be set when Am79C976 controller receives an RX_ER indication from the external PHY through the MII. 4 26 Reserved. 425 STP Start of Packet indicates that this is the first buffer used by the Am79C976 controller for this frame. If STP and ENP are both set to 1, the frame fits into a single buffer. Otherwise, the frame is spread over more than one buffer. When LAPPEN (CSR3, bit 5) is cleared to 0, STP is set by the Am79C976 controller and cleared by the host. When LAPPEN is set to 1, STP must be set by the host. 424 ENP End of Packet indicates that this is the last buffer used by the Am79C976 controller for this frame. It is used for data chaining buffers. If both STP and ENP are set, the frame fits into one buffer and there is no data chaining. ENP is set by the Am79C976 controller and cleared by the host. 4 23 Reserved. 422 PAM Physical Address Match is set by the Am79C976 controller when it accepts the received frame due to a match of the frame’s destination address with the content of the physical address register. PAM is valid only when ENP is set. PAM is set by the Am79C976 controller and cleared by the host. This bit does not exist when the Am79C976 controller is programmed to use 16-bit software structures for the descriptor ring entries (BCR20, bits 7-0, SWSTYLE is cleared to 0). |
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