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FG256 Datasheet(PDF) 12 Page - Actel Corporation |
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FG256 Datasheet(HTML) 12 Page - Actel Corporation |
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12 / 108 page ![]() SX-A Family FPGAs 1- 8 v5.3 Power-Up/Down and Hot Swapping SX-A I/Os are configured to be hot-swappable, with the exception of 3.3 V PCI. During power-up/down (or partial up/down), all I/Os are tristated. VCCA and VCCI do not have to be stable during power-up/down, and can be powered up/down in any order. When the SX-A device is plugged into an electrically active system, the device will not degrade the reliability of or cause damage to the host system. The device’s output pins are driven to a high impedance state until normal chip operating conditions are reached. Table 1-4 summarizes the VCCA voltage at which the I/Os behave according to the user’s design for an SX-A device at room temperature for various ramp-up rates. The data reported assumes a linear ramp-up profile to 2.5 V. For more information on power-up and hot-swapping, refer to the application note, Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications. Table 1-2 • I/O Features Function Description Input Buffer Threshold Selections • 5 V: PCI, TTL • 3.3 V: PCI, LVTTL • 2.5 V: LVCMOS2 (commercial only) Flexible Output Driver • 5 V: PCI, TTL • 3.3 V: PCI, LVTTL • 2.5 V: LVCMOS2 (commercial only) Output Buffer “Hot-Swap” Capability (3.3 V PCI is not hot swappable) • I/O on an unpowered device does not sink current • Can be used for “cold-sparing” Selectable on an individual I/O basis Individually selectable slew rate; high slew or low slew (The default is high slew rate). The slew is only affected on the falling edge of an output. Rising edges of outputs are not affected. Power-Up Individually selectable pull-ups and pull-downs during power-up (default is to power-up in tristate) Enables deterministic power-up of device VCCA and VCCI can be powered in any order Table 1-3 • I/O Characteristics for All I/O Configurations Hot Swappable Slew Rate Control Power-Up Resistor TTL, LVTTL, LVCMOS2 Yes Yes. Only affects falling edges of outputs Pull-up or pull-down 3.3 V PCI No No. High slew rate only Pull-up or pull-down 5 V PCI Yes No. High slew rate only Pull-up or pull-down Table 1-4 • Power-Up Time at which I/Os Become Active Supply Ramp Rate 0.25 V/ μs 0.025 V/μs 5 V/ms 2.5 V/ms 0.5 V/ms 0.25 V/ms 0.1 V/ms 0.025 V/ms Units μs μs ms msms msms ms A54SX08A 10 96 0.34 0.65 2.7 5.4 12.9 50.8 A54SX16A 10 100 0.36 0.62 2.5 4.7 11.0 41.6 A54SX32A 10 100 0.46 0.74 2.8 5.2 12.1 47.2 A54SX72A 10 100 0.41 0.67 2.6 5.0 12.1 47.2 |
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