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FG256 Datasheet(PDF) 37 Page - Actel Corporation |
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FG256 Datasheet(HTML) 37 Page - Actel Corporation |
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37 / 108 page ![]() SX-A Family FPGAs v5.3 2-17 Timing Characteristics Timing characteristics for SX-A devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input and output buffer characteristics are common to all SX-A family members. Internal routing delays are device-dependent. Design dependency means actual delays are not determined until after placement and routing of the user’s design are complete. The timing characteristics listed in this datasheet represent sample timing numbers of the SX-A devices. Design-specific delay values may be determined by using Timer or performing simulation after successful place-and-route with the Designer software. Critical Nets and Typical Nets Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most timing-critical paths. Critical nets are determined by net property assignment prior to placement and routing. Up to 6 percent of the nets in a design may be designated as critical, while 90 percent of the nets in a design are typical. Long Tracks Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or modules. Long tracks employ three to five antifuse connections. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically, up to 6 percent of nets in a fully utilized device require long tracks. Long tracks contribute approximately 4 ns to 8.4 ns delay. This additional delay is represented statistically in higher fanout routing delays. Timing Derating SX-A devices are manufactured with a CMOS process. Therefore, device performance varies according to temperature, voltage, and process changes. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. Temperature and Voltage Derating Factors Table 2-13 • Temperature and Voltage Derating Factors (Normalized to Worst-Case Commercial, TJ = 70°C, VCCA = 2.25 V) VCCA Junction Temperature (TJ) –55°C –40°C 0°C 25°C 70°C 85°C 125°C 2.250 V 0.790.800.870.89 1.001.04 1.14 2.500 V 0.740.750.820.83 0.940.97 1.07 2.750 V 0.680.690.750.77 0.870.90 0.99 |
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