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FG256 Datasheet(PDF) 36 Page - Actel Corporation |
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FG256 Datasheet(HTML) 36 Page - Actel Corporation |
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36 / 108 page ![]() SX-A Family FPGAs 2- 16 v5.3 Input Buffer Delays C-Cell Delays Cell Timing Characteristics Figure 2-6 • Input Buffer Delays PAD Y INBUF In 3 V 0 V 1.5 V Out GND 50% 1.5 V 50% VCC t INY t INY Figure 2-7 • C-Cell Delays S A B Y S, A, or B Out GND 50% Out GND GND 50% 50% 50% 50% 50% V CC V CC V CC t PD t PD t PD t PD Figure 2-8 • Flip-Flops (Positive Edge Triggered) D CLK CLR Q D CLK Q CLR t HPWH t WASYN t HD t SUD t HP t HPWL t RCO t CLR t RPWL t RPWH PRESET tPRESET PRESET |
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