FG256 datasheet(53/108 Pages) ACTEL

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SX-A Family FPGAs

v5.3

2-33

Table 2-27 • A54SX16A Timing Characteristics

(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 70°C)

Parameter

Description

–3 Speed1

–2 Speed

–1 Speed

Std. Speed

–F Speed

Units

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

5 V PCI Output Module Timing2

tDLH

Data-to-Pad Low to High

2.2

2.5

2.8

3.3

4.6

tDHL

Data-to-Pad High to Low

2.8

3.2

3.6

4.2

5.9

tENZL

Enable-to-Pad, Z to L

1.3

1.5

1.7

2.0

2.8

tENZH

Enable-to-Pad, Z to H

2.2

2.5

2.8

3.3

4.6

tENLZ

Enable-to-Pad, L to Z

3.0

3.5

3.9

4.6

6.4

tENHZ

Enable-to-Pad, H to Z

2.8

3.2

3.6

4.2

5.9

dTLH

Delta Low to High

0.016

0.02

0.022

0.032

ns/pF

dTHL

Delta High to Low

0.026

0.03

0.032

0.04

0.052

ns/pF

5 V TTL Output Module Timing4

tDLH

Data-to-Pad Low to High

2.2

2.5

2.8

3.3

4.6

tDHL

Data-to-Pad High to Low

2.8

3.2

3.6

4.2

5.9

tDHLS

Data-to-Pad High to Low—low slew

6.7

7.7

8.7

10.2

14.3

tENZL

Enable-to-Pad, Z to L

2.1

2.4

2.7

3.2

4.5

tENZLS

Enable-to-Pad, Z to L—low slew

7.4

8.4

9.5

11.0

15.4

tENZH

Enable-to-Pad, Z to H

1.9

2.2

2.5

2.9

4.1

tENLZ

Enable-to-Pad, L to Z

3.6

4.2

4.7

5.6

7.8

tENHZ

Enable-to-Pad, H to Z

2.5

2.9

3.3

3.9

5.4

dTLH

Delta Low to High

0.014

0.017

0.023

0.031

ns/pF

dTHL

Delta High to Low

0.023

0.029

0.031

0.037

0.051

ns/pF

dTHLS

Delta High to Low—low slew

0.043

0.046

0.057

0.066

0.089

ns/pF

Notes:

1. All –3 speed grades have been discontinued.

2. Delays based on 50 pF loading.

3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:

Slew Rate [V/ns] = (0.1*VCCI – 0.9*VCCI)/ (Cload * dT[LH|HL|HLS])

where Cload is the load capacitance driven by the I/O in pF

dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.

4. Delays based on 35 pF loading.

FG256 Datasheet(PDF) 53 Page - Actel Corporation

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