FG256 datasheet(43/108 Pages) ACTEL

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SX-A Family FPGAs

v5.3

2-23

Table 2-18 • A54SX08A Timing Characteristics

(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.3 V, TJ = 70°C)

Parameter

Description

–2 Speed

–1 Speed

Std. Speed

–F Speed

Units

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

2.5 V LVCMOS Output Module Timing1,2

tDLH

Data-to-Pad Low to High

3.9

4.4

5.2

7.2

tDHL

Data-to-Pad High to Low

3.0

3.4

3.9

5.5

tDHLS

Data-to-Pad High to Low—low slew

13.3

15.1

17.7

24.8

tENZL

Enable-to-Pad, Z to L

2.8

3.2

3.7

5.2

tENZLS

Data-to-Pad, Z to L—low slew

13.7

15.5

18.2

25.5

tENZH

Enable-to-Pad, Z to H

3.9

4.4

5.2

7.2

tENLZ

Enable-to-Pad, L to Z

2.5

2.8

3.3

4.7

tENHZ

Enable-to-Pad, H to Z

3.0

3.4

3.9

5.5

dTLH

Delta Low to High

0.037

0.043

0.051

0.071

ns/pF

dTHL

Delta High to Low

0.017

0.023

0.037

ns/pF

dTHLS

Delta High to Low—low slew

0.06

0.071

0.086

0.117

ns/pF

Note:

1. Delays based on 35 pF loading.

2. The equivalent I/O Attribute Editor settings for 2.5 V LVCMOS is 2.5 V LVTTL in the software.

3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:

Slew Rate [V/ns] = (0.1*VCCI – 0.9*VCCI)/ (Cload * dT[LH|HL|HLS])

where Cload is the load capacitance driven by the I/O in pF

dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.

FG256 Datasheet(PDF) 43 Page - Actel Corporation

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