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FG256 Datasheet(PDF) 44 Page - Actel Corporation

Part # FG256
Description  SX-A Family FPGAs
PDF  108 Pages
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

FG256 Datasheet(HTML) 44 Page - Actel Corporation

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SX-A Family FPGAs
2- 24
v5.3
Table 2-19 • A54SX08A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70°C)
Parameter
Description
–2 Speed
–1 Speed
Std. Speed
–F Speed
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
3.3 V PCI Output Module Timing1
tDLH
Data-to-Pad Low to High
2.2
2.4
2.9
4.0
ns
tDHL
Data-to-Pad High to Low
2.3
2.6
3.1
4.3
ns
tENZL
Enable-to-Pad, Z to L
1.7
1.9
2.2
3.1
ns
tENZH
Enable-to-Pad, Z to H
2.2
2.4
2.9
4.0
ns
tENLZ
Enable-to-Pad, L to Z
2.8
3.2
3.8
5.3
ns
tENHZ
Enable-to-Pad, H to Z
2.3
2.6
3.1
4.3
ns
dTLH
2
Delta Low to High
0.03
0.03
0.04
0.045
ns/pF
dTHL
2
Delta High to Low
0.015
0.015
0.015
0.025
ns/pF
3.3 V LVTTL Output Module Timing3
tDLH
Data-to-Pad Low to High
3.0
3.4
4.0
5.6
ns
tDHL
Data-to-Pad High to Low
3.0
3.3
3.9
5.5
ns
tDHLS
Data-to-Pad High to Low—low slew
10.4
11.8
13.8
19.3
ns
tENZL
Enable-to-Pad, Z to L
2.6
2.9
3.4
4.8
ns
tENZLS
Enable-to-Pad, Z to L—low slew
18.9
21.3
25.4
34.9
ns
tENZH
Enable-to-Pad, Z to H
3
3.4
4
5.6
ns
tENLZ
Enable-to-Pad, L to Z
3.3
3.7
4.4
6.2
ns
tENHZ
Enable-to-Pad, H to Z
3
3.3
3.9
5.5
ns
dTLH
2
Delta Low to High
0.03
0.03
0.04
0.045
ns/pF
dTHL
2
Delta High to Low
0.015
0.015
0.015
0.025
ns/pF
dTHLS
2
Delta High to Low—low slew
0.053
0.067
0.073
0.107
ns/pF
Notes:
1. Delays based on 10 pF loading and 25
Ω resistance.
2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:
Slew Rate [V/ns] = (0.1*VCCI – 0.9*VCCI)/ (Cload * dT[LH|HL|HLS])
where Cload is the load capacitance driven by the I/O in pF
dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
3. Delays based on 35 pF loading.



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