FG256 datasheet(15/108 Pages) ACTEL

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SX-A Family FPGAs

v5.3

1-11

Probing Capabilities

SX-A devices also provide an internal probing capability

that is accessed with the JTAG pins. The Silicon Explorer II

diagnostic hardware is used to control the TDI, TCK, TMS,

and TDO pins to select the desired nets for debugging.

The user assigns the selected internal nets in Actel Silicon

Explorer II software to the PRA/PRB output pins for

observation. Silicon Explorer II automatically places the

device into JTAG mode. However, probing functionality is

only activated when the TRST pin is driven high or left

floating, allowing the internal pull-up resistor to pull

TRST High. If the TRST pin is held Low, the TAP controller

remains in the Test-Logic-Reset state so no probing can

be performed. However, the user must drive the TRST pin

High or allow the internal pull-up resistor to pull TRST

High.

When selecting the Reserve Probe Pin box as shown in

Figure 1-12 on page 1-9, direct the layout tool to reserve

the PRA and PRB pins as dedicated outputs for probing.

This Reserve option is merely a guideline. If the designer

assigns user I/Os to the PRA and PRB pins and selects the

Reserve

Probe

Pin option, Designer Layout will

override the Reserve Probe Pin option and place the

user I/Os on those pins.

To allow probing capabilities, the security fuse must not

be programmed. Programming the security fuse disables

the JTAG and probe circuitry. Table 1-9 summarizes the

possible device configurations for probing once the

device leaves the Test-Logic-Reset JTAG state.

Table 1-9 • Device Configuration Options for Probe Capability (TRST Pin Reserved)

JTAG Mode

TRST1

Security Fuse Programmed

PRA, PRB2

TDI, TCK, TDO2

Dedicated

Low

User I/O3

JTAG Disabled

High

Probe Circuit Outputs

JTAG I/O

Flexible

Low

User I/O3

High

Probe Circuit Outputs

JTAG I/O

Yes

Probe Circuit Secured

Notes:

1. If the TRST pin is not reserved, the device behaves according to TRST = High as described in the table.

2. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, input

signals will not pass through these pins and may cause contention.

3. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically tristated by

the Designer software.

FG256 Datasheet(PDF) 15 Page - Actel Corporation

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