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FG256 Datasheet(PDF) 64 Page - Actel Corporation |
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FG256 Datasheet(HTML) 64 Page - Actel Corporation |
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64 / 108 page ![]() SX-A Family FPGAs 2- 44 v5.3 Table 2-36 • A54SX72A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.25 V, TJ = 70°C) Parameter Description –3 Speed* –2 Speed –1 Speed Std. Speed –F Speed Units Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Dedicated (Hardwired) Array Clock Networks tHCKH Input Low to High (Pad to R-cell Input) 1.6 1.9 2.1 2.5 3.8 ns tHCKL Input High to Low (Pad to R-cell Input) 1.6 1.9 2.1 2.5 3.8 ns tHPWH Minimum Pulse Width High 1.5 1.7 2.0 2.3 3.2 ns tHPWL Minimum Pulse Width Low 1.5 1.7 2.0 2.3 3.2 ns tHCKSW Maximum Skew 1.4 1.6 1.8 2.1 3.3 ns tHP Minimum Period 3.0 3.4 4.0 4.6 6.4 ns fHMAX Maximum Frequency 333 294 250 217 156 MHz Routed Array Clock Networks tRCKH Input Low to High (Light Load) (Pad to R-cell Input) 2.3 2.6 2.9 3.4 4.8 ns tRCKL Input High to Low (Light Load) (Pad to R-cell Input) 2.8 3.2 3.7 4.3 6.0 ns tRCKH Input Low to High (50% Load) (Pad to R-cell Input) 2.4 2.8 3.2 3.7 5.2 ns tRCKL Input High to Low (50% Load) (Pad to R-cell Input) 2.9 3.3 3.8 4.5 6.2 ns tRCKH Input Low to High (100% Load) (Pad to R-cell Input) 2.6 3.0 3.4 4.0 5.6 ns tRCKL Input High to Low (100% Load) (Pad to R-cell Input) 3.1 3.6 4.0 4.7 6.6 ns tRPWH Minimum Pulse Width High 1.5 1.7 2.0 2.3 3.2 ns tRPWL Minimum Pulse Width Low 1.5 1.7 2.0 2.3 3.2 ns tRCKSW Maximum Skew (Light Load) 1.9 2.2 2.5 3.0 4.1 ns tRCKSW Maximum Skew (50% Load) 1.8 2.1 2.4 2.8 3.9 ns tRCKSW Maximum Skew (100% Load) 1.8 2.1 2.4 2.8 3.9 ns Quadrant Array Clock Networks tQCKH Input Low to High (Light Load) (Pad to R-cell Input) 2.6 3.0 3.4 4.0 5.6 ns tQCHKL Input High to Low (Light Load) (Pad to R-cell Input) 2.6 3.0 3.3 3.9 5.5 ns tQCKH Input Low to High (50% Load) (Pad to R-cell Input) 2.8 3.2 3.6 4.3 6.0 ns tQCHKL Input High to Low (50% Load) (Pad to R-cell Input) 2.8 3.2 3.6 4.2 5.9 ns Note: *All –3 speed grades have been discontinued. |
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