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FG256 Datasheet(PDF) 35 Page - Actel Corporation |
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FG256 Datasheet(HTML) 35 Page - Actel Corporation |
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35 / 108 page  SX-A Family FPGAs v5.3 2-15 Output Buffer Delays AC Test Loads Figure 2-4 • Output Buffer Delays To AC Test Loads (shown below) PAD D E TRIBUFF In GND 50% Out 1.5 V 50% 1.5 V En GND 50% Out 1.5 V 50% 10% En GND 50% Out GND 1.5 V 50% 90% VOL VOL V CC V CC V CC V CC V OH t ENZH t ENHZ t ENZL t ENLZ t DLH Figure 2-5 • AC Test Loads 35 pF VCC GND 35 pF VCC GND 5 pF R to VCC for t PZL R to GND for tPZH R = 1 k Ω R to VCC for tPZL R to GND for tPZH R = 1 k Ω To the Output Under Test To the Output Under Test To the Output Under Test Load 1 (Used to measure propagation delay) Load 2 (Used to measure enable delays) Load 3 (Used to measure disable delays) |
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