FG256 datasheet(34/108 Pages) ACTEL

34 / 108 page

SX-A Family FPGAs

2- 14

v5.3

SX-A Timing Model

Sample Path Calculations

Hardwired Clock

Routed Clock

Note: *Values shown for A54SX72A, –2, worst-case commercial conditions at 5 V PCI with standard place-and-route.

Figure 2-3 • SX-A Timing Model

Input Delays

Internal Delays

Predicted

Routing

Delays

Output Delays

I/O Module

INYH = 0.6 ns

RD2 = 0.5 ns

RD1 = 0.3 ns

Combinatorial

Cell

I/O Module

DHL = 3.9 ns

RD8 = 1.5 ns

RD4 = 0.9 ns

RD1 = 0.3 ns

PD = 1.1 ns

I/O Module

DHL = 3.9 ns

RD1 = 0.3 ns

RCO= 0.8 ns

I/O Module

INYH = 0.6 ns

ENZL= 1.5 ns

SUD = 0.8 ns

HD = 0.0 ns

SUD = 0.8 ns

HD = 0.0 ns

RCKH = 3.0 ns

(100% Load)

Cell

Routed

Clock

RD1 = 0.3 ns

RCO= 0.8 ns

HCKH= 1.8 ns

Cell

Hardwired

Clock

I/O Module

DHL = 3.9 ns

ENZL= 1.5 ns

External Setup

= (tINYH + tRD1 + tSUD) – tHCKH

= 0.6 + 0.3 + 0.8 - 1.8 = – 0.1 ns

Clock-to-Out (Pad-to-Pad) = tHCKH + tRCO + tRD1 + tDHL

= 1.8 + 0.8 + 0.3 + 3.9 = 6.8 ns

External Setup

= (tINYH + tRD1 + tSUD) – tRCKH

= 0.6 + 0.3 + 0.8 - 3.0 = –1.3 ns

Clock-to-Out (Pad-to-Pad) = tRCKH + tRCO + tRD1 + tDHL

= 3.0 + 0.8 + 0.3 + 3.9 = 8.0 ns

FG256 Datasheet(PDF) 34 Page - Actel Corporation

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