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FG256 Datasheet(PDF) 62 Page - Actel Corporation

Part # FG256
Description  SX-A Family FPGAs
PDF  108 Pages
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

FG256 Datasheet(HTML) 62 Page - Actel Corporation

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SX-A Family FPGAs
2- 42
v5.3
Table 2-35 • A54SX72A Timing Characteristics
(Worst-Case Commercial Conditions, VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70°C)
Parameter
Description
–3 Speed1
–2 Speed
–1 Speed
Std. Speed
–F Speed
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
C-Cell Propagation Delays2
tPD
Internal Array Module
1.0
1.1
1.3
1.5
2.0
ns
Predicted Routing Delays3
tDC
FO
=
1
Routing
Delay,
Direct
Connect
0.1
0.1
0.1
0.1
0.1
ns
tFC
FO = 1 Routing Delay, Fast Connect
0.3
0.3
0.3
0.4
0.6
ns
tRD1
FO = 1 Routing Delay
0.3
0.3
0.4
0.5
0.7
ns
tRD2
FO = 2 Routing Delay
0.4
0.5
0.6
0.7
1
ns
tRD3
FO = 3 Routing Delay
0.5
0.7
0.8
0.9
1.3
ns
tRD4
FO = 4 Routing Delay
0.7
0.9
1
1.1
1.5
ns
tRD8
FO = 8 Routing Delay
1.2
1.5
1.7
2.1
2.9
ns
tRD12
FO = 12 Routing Delay
1.7
2.2
2.5
3
4.2
ns
R-Cell Timing
tRCO
Sequential Clock-to-Q
0.7
0.8
0.9
1.1
1.5
ns
tCLR
Asynchronous Clear-to-Q
0.6
0.7
0.7
0.9
1.2
ns
tPRESET
Asynchronous Preset-to-Q
0.7
0.8
0.8
1.0
1.4
ns
tSUD
Flip-Flop Data Input Set-Up
0.7
0.8
0.9
1.0
1.4
ns
tHD
Flip-Flop Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tWASYN
Asynchronous Pulse Width
1.3
1.5
1.7
2.0
2.8
ns
tRECASYN
Asynchronous Recovery Time
0.3
0.4
0.4
0.5
0.7
ns
tHASYN
Asynchronous Hold Time
0.3
0.3
0.3
0.4
0.6
ns
tMPW
Clock Minimum Pulse Width
1.5
1.7
2.0
2.3
3.2
ns
Input Module Propagation Delays
tINYH
Input Data Pad to Y High 2.5 V
LVCMOS
0.6
0.7
0.8
0.9
1.3
ns
tINYL
Input Data Pad to Y Low 2.5 V
LVCMOS
0.8
1.0
1.1
1.3
1.7
ns
tINYH
Input Data Pad to Y High 3.3 V PCI
0.6
0.7
0.7
0.9
1.2
ns
tINYL
Input Data Pad to Y Low 3.3 V PCI
0.7
0.8
0.9
1.0
1.4
ns
tINYH
Input Data Pad to Y High 3.3 V
LVTTL
0.7
0.7
0.8
1.0
1.4
ns
tINYL
Input Data Pad to Y Low 3.3 V LVTTL
1.0
1.2
1.3
1.5
2.1
ns
Notes:
1. All –3 speed grades have been discontinued.
2. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.



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