LM98714 datasheet(23/115 Pages) TI1

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CLAMP

SAMPLE

VCLP

HOLD

PAR

Optical Black Pixels

Dummy Pixels

Invalid

Pixels

Valid Pixels

SAMPLE

CLPIN

GATED

CLPIN

Auto CLPIN Position Register

Page 0, Reg. 6, Bits[7:0]

Input Clamp Control Register

Page 0, Reg. 5, Bits[3:2]

(Auto CLPIN Width)

LM98714

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SNAS254A – OCTOBER 2006 – REVISED JANUARY 2014

Figure 10. Typical CCD Waveform and LM98714 Input Clamp Signal (CLPIN)

Figure 11. Sample and Hold Mode Simplified Input Diagram

Proper DC biasing of the CCD waveform in Sample and Hold mode is critical for realizing optimal operating

conditions. In Sample/Hold mode, the Signal Level of the CCD waveform is compared to the DC voltage on the

VCLP pin. In order to fully utilize the range of the input circuitry, it is desirable to cause the Black Level signal

voltage to be as close to the VCLP voltage as possible, resulting in a near zero scale output for Black Level

pixels.

In Sample/Hold Mode, the DC bias point of the input pin is typically set by actuating the input clamp switch (see

Figure 9) during optical black pixels which connects the input pins to the VCLP pin DC voltage. The signal

controlling this switch is an auto-generated pulse, CLPIN. CLPIN is generated with a programmable pixel delay

with respect to SH and a programmable pixel width. These parameters are available through the serial interface

control registers.

Actuating the input clamp will force the average value of the CCD waveform to be centered around the VCLP DC

voltage. During Optical Black Pixels, the CCD output has roughly three components. The first component of the

pixel is a “Reset Noise” peak followed by the Reset (or Pedestal) Level voltage, then finally the Black Level

voltage signal. Taking the average of these signal components will result in a final “clamped” DC bias point that

is close to the Black Level signal voltage.

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