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LM98714 Datasheet(PDF) 16 Page - Texas Instruments |
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LM98714 Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 115 page  OS R OS G OS B Input Bias/ Clamping Input Bias/ Clamping Input Bias/ Clamping CDS or Sample/Hold Amplifier CDS or Sample/Hold Amplifier CDS or Sample/Hold Amplifier PGA PGA PGA 3:1 MUX 5:1 MUX COLOR1DAC[9:0] COLOR2DAC[9:0] COLOR3DAC[9:0] COLOR4DAC[9:0] COLOR5DAC[9:0] COLOR2DAC[9:0] COLOR3DAC[9:0] 5:1 MUX COLOR1PGA[7:0] COLOR2PGA[7:0] COLOR3PGA[7:0] COLOR4PGA[7:0] COLOR5PGA[7:0] COLOR2PGA[7:0] COLOR3PGA[7:0] Black Level Offset DAC Black Level Offset DAC Black Level Offset DAC LM98714 SNAS254A – OCTOBER 2006 – REVISED JANUARY 2014 www.ti.com Modes of Operation MODE 3 - THREE CHANNEL INPUT/SYNCHRONOUS PIXEL SAMPLING In Mode 3, the OSR, OSG, and OSB input channels are sampled synchronously. The sampled input signals are then processed in parallel through their respective channels with each channel offset and gain adjusted by their respective control registers. The signals are then routed through a 3-1 MUX to the ADC. The order in which pixels are processed through the MUX to the ADC is programmable (OSR-OSG-OSB, or OSB-OSG-OSR) and is synchronized by the SH pulse. Figure 5. Synchronous Three Channel Pixel Mode Signal Routing Table 1. Mode 3 Operating Details Detail Channels Active OSB & OSG & OSR 3 channel synchronous pixel sampling. Channel Sample Rate 15 MSPS per Channel (max) ADC Sample Rate 45 MSPS (max) Internal 3x Clock Selected 3:01 fINCLK = 15MHz (max) fADC: fINCLK Internal 1x Clock Selected 1:01 fINCLK = 45MHz (max) SH Signal --> R-G-B-R-G-B-R-G-B → Output Sequencing or SH Signal --> B-G-R-B-G-R-B-G-R → 16 Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM98714 |
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