Electronic Components Datasheet Search
  English  ▼

X  

LM98714 Datasheet(PDF) 38 Page - Texas Instruments

Click here to check the latest version.
Part # LM98714
Description  LM98714 Three Channel, 16-Bit, 45 MSPS Analog Front End with LVDS/CMOS Output
PDF  115 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

LM98714 Datasheet(HTML) 38 Page - Texas Instruments

Back Button LM98714 Datasheet HTML 34Page - Texas Instruments LM98714 Datasheet HTML 35Page - Texas Instruments LM98714 Datasheet HTML 36Page - Texas Instruments LM98714 Datasheet HTML 37Page - Texas Instruments LM98714 Datasheet HTML 38Page - Texas Instruments LM98714 Datasheet HTML 39Page - Texas Instruments LM98714 Datasheet HTML 40Page - Texas Instruments LM98714 Datasheet HTML 41Page - Texas Instruments LM98714 Datasheet HTML 42Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 38 / 115 page
background image
LM98714
SNAS254A – OCTOBER 2006 – REVISED JANUARY 2014
www.ti.com
The loop is intended to be used prior to scanning the page or during the first several lines at the beginning of a
scan. The loop calibrates the channel offset such that the ADC outputs the desired code for Optical Black Pixels.
In automatic mode, the pixels used to calibrate the offset should be Optical Black pixels represented by the
internal “BLKCLP” pulse in Figure 31.
BLACK LEVEL OFFSET DAC
The offset level registers store the DAC value required to meet the respective channel’s black level output. While
using the Auto Black Level Correction Loop, the DAC registers are re-written as required every line the loop is
enabled.
BLACK LEVEL CLAMP (BLKCLP)
The BLKCLP pulse can be synchronized by either the falling edge of the SH pulse or the CLPIN pulse (both
shown in Figure 31). The automatic BLKCLP pulse will begin “n” number of pixel periods after the falling edge of
the reference pulse where “n” is the Auto Black Level Clamp Position register. The reference point is
programmed by the BLKCLP Mode Select Bits[1:0] within the Black Level Clamp Control register. The BLKCLP
pulse should not be programmed coincident to the CLPIN pulse (if the CLPIN pulse is being used).
Figure 31. Black Level Correction Timing
38
Submit Documentation Feedback
Copyright © 2006–2014, Texas Instruments Incorporated
Product Folder Links: LM98714



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com