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LM98714 Datasheet(PDF) 95 Page - Texas Instruments |
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LM98714 Datasheet(HTML) 95 Page - Texas Instruments |
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95 / 115 page ![]() LM98714 www.ti.com SNAS254A – OCTOBER 2006 – REVISED JANUARY 2014 Table 16. (continued) Address Register Default Page Bit(s) Description (Binary) Title (Binary) These registers set which timing signal is present on the respective CLKn output pin. Setting CLKn = 0000 Tristate 0001 PIX1 0010 PIX2 [7:4] CLK 0011 PIX3 9 0100 PIX4 0101 PIX5 Output 0110 PIX6 Mapping 0000 3 0 0100 CLK9/CLK 0000 0111 PIX7 10 1000 PIX8 1001 LAMPR 1010 LAMPG [3:0] 1011 LAMPB CLK 1100 LAMPIR1 10 1101 LAMPIR2 1110 MODE 1111 SH LAMPR Normal State [7] 0 = Low, 1 = High LAMPG Normal State [6] 0 = Low, 1 = High LAMPB Normal State [5] 0 = Low, 1 = High Illumination Mode (see LampIR1 Normal State 0000 3 0 0101 also AFE [4] 0000 0 = Low, 1 = High color modes) LampIR2 Normal State [3] 0 = Low, 1 = High [2:1] Reserved SH/LAMP Overlap Enable [0] 0 Disabled 1 Overlap Enabled Copyright © 2006–2014, Texas Instruments Incorporated Submit Documentation Feedback 95 Product Folder Links: LM98714 |
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