LM98714 datasheet(14/115 Pages) TI1

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LM98714

SNAS254A – OCTOBER 2006 – REVISED JANUARY 2014

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System Overview

INTRODUCTION

The LM98714 is a 16-bit, three-input, complete Analog Front End (AFE) for digital color copier and Multi-Function

Peripheral (MFP) applications. The system block diagram of the LM98714, shown in Figure 2 highlights the main

features of the device. Each input has its own Input Bias and Clamping Network which are routed through a

selectable Sample/Hold (S/H) or Correlated Double Sampler (CDS) amplifier. A +/-9-Bit Offset DAC applies

independent offset correction for each channel. A -3 to 17.9dB Programmable Gain Amplifier (PGA) applies

independent gain correction for each channel. The LM98714 also provides independent Digital Black Level

Correction Feedback Loops for each channel. The Black Level Correction Loop can be configured to run in

Manual Mode (where the user inputs their own values of DAC offset) or in Automatic Mode where the LM98714

calculates each channel’s Offset DAC value during optical black pixels and then adjusts the Offset register

accordingly. The signals are routed to a single high performance 16-bit, 45MHz analog-to-digital converter.

MODES OF OPERATION INTRODUCTION

The LM98714 can be configured to operate in several different operating modes. The following sections are a

brief introduction to these modes of operation. A more rigorous explanation of the operating modes is contained

in the Modes of Operation section. including input sampling diagrams for each mode as well as a description of

the operating conditions.

Mode 3 - Three Channel Input/Synchronous Pixel Sampling

OSB, OSG, and OSR inputs are sampled synchronously at a pixel rate. The sampled signals are processed with

each channel’s offset and gain adjusted independently via the control registers. The order in which pixels are

processed from the input to the ADC is fully programmable and is synchronized by the SH pulse. In this mode,

the maximum channel speed is 15MSPS per channel with the ADC running at 45MSPS yielding a three color

throughput of 45MSPS.

Mode 2 - Two Channel Input/Synchronous Pixel Sampling

Mode 2 is useful for CCD sensors with a Black and White mode with Even and Odd outputs. In its default

configuration, Mode 2 samples the Even output via the OSB channel input, and the Odd output via the OSG

channel input. Sampling of the Even and Odd pixels is performed synchronously at a maximum sample rate of

22.5MSPS per input with the ADC running at 45MSPS.

Mode 1a - One Channel Input/One, Two, Three, Four, or Five Color Sequential Line Sampling

In Mode 1a, all pixels are processed through a single input (OSR, OSG, or OSB) chosen through the control

programmable through the control register. If more than one color is being sent to the input, the user can

configure the OSR channel to utilize up to five offset and gain coefficients for up to five different lines of color

pixels. The SH pulse at the beginning of each line sequences the DAC and PGA coefficients as configured in the

control registers. In this mode, the maximum channel speed is 30MSPS per channel with the ADC running at

30MSPS.

Mode 1b - One Channel Input Per Line/Sequential Line (Input) Sampling/Three Channel Processing

In Mode 1b the OSR, OSG, and OSB inputs are sampled one input per line with the input selection being

sequenced to the next color by an SH pulse. This mode is useful with sensors that output whole lines of pixels of

a single color. The order in which the inputs are sampled is fully programmable. Sequencing from one channel to

the next is triggered by the SH pulse. The first SH pulse after this mode is set (or reset) sets up the first

programmed input for gain and offset and initiates sampling through that input alone. The next SH pulse switches

the active input to the second channel indicated by the configuration registers. This sequencing with SH pulses

continues to the third input and then continuously loops through the inputs. In this mode, the maximum channel

speed is 30MSPS per channel with the ADC running at 30MSPS.

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