LM98714 datasheet(79/115 Pages) TI1

79 / 115 page

LM98714

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SNAS254A – OCTOBER 2006 – REVISED JANUARY 2014

Table 16. (continued)

Address

Default

Page

Bit(s)

Description

(Binary)

Title

(Binary)

[7:0]

Main Configuration 4

[7:4]

Not Used

[3]

Upcount Enable

LVDS Test Mode. Activates LVDS test pattern output (when in LVDS output mode only).

000 Normal operation, no test pattern output (Default)

Main

0000

001 Test pattern 1: Alternating pattern between 0x155555 and 0x0AAAAA

0 0100

Configurati

0000

010 Test pattern 2: If Upcount Enable Bit set, count from 21h000000 to 21h 1FFFFF

on 4

[2:0]

011 Test pattern 3. Output Static Count value found represented by the three Upcounter Registers found on page

Reg 0x14 Bits[4:0] = Count Values 5 MSBs

Reg 0x13 Bits[7:0] = Count Values 8 Middle Bits

Reg 0x12 Bits[7:0] = Count Values 8 LSBs

[7:0]

Input Clamp Control (CLPIN) Configuration Register

[7:4]

Reserved

Auto CLPIN Width. Width in Pixels of the Auto generated CLPIN pulse.

00 4 Pixels (Default)

[3:2]

01 8 Pixels

10 16 Pixels

11 32 Pixels

Input

0000

0 0101

Clamp

Auto CLPIN Enable.

0000

Control

0 Auto CLPIN Disabled

[1]

CLPIN Pulse generation Disabled (Default)

1 Auto CLPIN

CLPIN generated internally with a programmable delay from SH

CLPIN Gating Enable.

[0]

0 Auto CLPINGATED not gated by SAMPLE (default)

1 Auto CLPINGATED gated by SAMPLE (= logical and of CLPIN and SAMPLE)

[7:0]

Auto CLPIN Pulse Position Register

Auto

0010

0 0110

CLPIN

Auto CLPIN Pulse Position. Number of pixels in which Auto CLPIN pulse is delayed, relative to the falling edge of

0111

[7:0]

Position

SH.

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