LM98714 datasheet(29/115 Pages) TI1

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INCLK (Pixel Rate)

φ1A output from LM98714

CCD Timing generator

φ1A input at CCD

(after inverter)

Pixel output from CCD

The LM98714 internal clock tree creates a small amount of

delay in the CCD Timing generator outputs.

Application board discrete logic also creates propagation delay

with respect to the input clock.

Finally, the CCD propagation delay further shifts the Pixel

signal input to the LM98714 from the input clock.

PIXPHASE0

(default “coarse’ pixel phase)

CLAMP

(internal pixel reference

level sampling clock)

SAMPLE

(internal pixel data level

sampling clock)

Default CLAMP fine

adjust window

Default CLAMP fine

adjust window

Default SAMPLE

fine adjust window

Maximum fine adjust

not good enough for

default PIXPHASE,

CLAMP and SAMPLE

are too early due to

propagation delays.

LM98714

www.ti.com

SNAS254A – OCTOBER 2006 – REVISED JANUARY 2014

In a real system however, propagation delays exist in all stages of the signal chain. These propagation delays

will lead to a shift in the CCD Pixel outputs with respect to the LM98714 input clock. The phase shift of the CCD

Pixel output, demonstrated in Figure 18, can lead to significant sample timing issues if not properly corrected.

Figure 18. CCD Output Phase Shift in a Real Application

In the default mode, the LM98714 sampling is performed during a clock period whose phase is aligned with the

input clock (ignoring any clock tree skew for the moment). The actual sampling clocks are adjustable within the

clock period, as shown in Figure 18 (shown for CDS mode in the diagram) and further described in the Internal

Sample Timing section. As shown in the diagram, the delay of the CCD Pixel output is shifted far enough that the

fine CLAMP and SAMPLE clocks cannot be placed in a stable portion of the waveform. To remedy this situation,

the LM98714’s Coarse Pixel Phase Alignment feature allows the designer to shift the entire phase of the analog

front end with respect to the input clock. This allows the designer to choose one of four sampling phases which

best matches the delay in the external circuitry. Once the “Coarse Pixel Phase” has been chosen, the designer

can then fine tune the sampling clocks using the fine adjustment (see Internal Sample Timing)

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