LM98714 datasheet(28/115 Pages) TI1

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INCLK (Pixel Rate)

φ1A output from LM98714

CCD Timing generator

φ1A input at CCD

(after inverter)

Pixel output from CCD

By default, the LM98714's internal sampling clocks (CLAMP and SAMPLE) are adjustable

within PIXPHASE0, an internal pixel rate clock which is in phase with the input clock.

In an ideal application, the LM98714 CCD Timing generator outputs would be phase aligned

with the input clock;

the output of discrete logic on the application board would have no signal skew or delay;

and the CCD pixel output would have no delay with respect to

its input clock.

PIXPHASE0

(default “coarse’ pixel phase)

CLAMP

(internal pixel reference

level sampling clock)

SAMPLE

(internal pixel data level

sampling clock)

CLAMP and SAMPLE fine adjust window

Ideal CCD reference

level sample point

Ideal CCD data level

sample point

LM98714

SNAS254A – OCTOBER 2006 – REVISED JANUARY 2014

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In an ideal application, depicted in Figure 17, the Pixel output signal would be in phase with the timing signals

that drove the CCD. The LM98714 input sampling clocks (CLAMP and SAMPLE) are adjustable within a pixel

period. By default, the pixel period (or pixel “phase”) is defined to be in line with the input clock. As shown in the

ideal case in Figure 17, CLAMP and SAMPLE can be properly adjusted to their ideal positions within the pixel

phase, shown below at the stable region near the end of the pedestal and data phases.

Figure 17. Clock Alignment in an Ideal Application

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LM98714 Datasheet(PDF) 28 Page - Texas Instruments