LM98714 datasheet(15/115 Pages) TI1

15 / 115 page

LM98714

www.ti.com

SNAS254A – OCTOBER 2006 – REVISED JANUARY 2014

INPUT CLOCK INTRODUCTION

The clock input to the LM98714 can be a differential LVDS clock on the INCLK+ and INCLK- pins or a CMOS

level clock applied to the INCLK+ pin with the INCLK- pin connected to DGND. The external clock signal format

is auto sensed internally. In addition to the two available level formats, the input clock can be applied at the Pixel

frequency (PIXCLK) or at the ADC frequency (ADCCLK). The LM98714 can perform internal clock multiplication

when a Pixel frequency clock is applied, or no multiplication when an ADC frequency clock is applied. The

internal configuration registers need to be written to perform the proper setup of the input clock. The available

input clock configurations for each operating mode is outlined in the following table.

Internal

INCLK

AFE Mode

Input Clock Type

Configuration Register Settings

Multiplier

Max Freq.

INCLK = Pixel Freq. (PIXCLK)

15MHz

PIXCLK Configuration: Main Config Reg 1, Bit[2] = 1'b1

Mode 3

INCLK = ADC Freq. (ADCCLK)

45MHz

ADCCLK Configuration: Main Config Reg 1, Bit[2] = 1'b0

INCLK = Pixel Freq. (PIXCLK)

22.5MHz

PIXCLK Configuration: Main Config Reg 1, Bit[2] = 1'b1

Mode 2

INCLK = ADC Freq. (ADCCLK)

45MHz

ADCCLK Configuration: Main Config Reg 1, Bit[2] = 1'b0

INCLK = Pixel Freq. = ADC Freq

Mode 1

30MHz

Main Config Reg 1, Bit[2] = 1'bx

(ADCCLK = PIXCLK in Mode 1)

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