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LM98714 Datasheet(PDF) 12 Page - Texas Instruments

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Part # LM98714
Description  LM98714 Three Channel, 16-Bit, 45 MSPS Analog Front End with LVDS/CMOS Output
PDF  115 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

LM98714 Datasheet(HTML) 12 Page - Texas Instruments

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LM98714
SNAS254A – OCTOBER 2006 – REVISED JANUARY 2014
www.ti.com
AC Timing Specifications
The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified.
Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C.
Symbol
Parameter
Conditions
Min
Typ(1)
Max
Units
Input Clock Timing Specifications
15 (Mode 3)
INCLK = PIXCLK
22.5 (Mode 2)
MHz
(Pixel Rate Clock)
30 (Mode 1)
fINCLK
Input Clock Frequency
45 (Mode 3)
INCLK = ADCCLK
5
45 (Mode 2)
MHz
(ADC Rate Clock)
30 (Mode 1)
Tdc
Input Clock Duty Cycle
40/60
50/50
60/40
%
Full Channel Latency Specifications
SH out to First Sampled Pixel
PIXPHASE0
3
Figure 19 (Mode 3)
PIXPHASE1
3 3/7
tSHFP
TADC
Figure 20 (Mode 2)
PIXPHASE2
4
Figure 21 (Mode 1)
PIXPHASE3
4 3/7
PIXPHASE0
19
3 Channel Mode Pipeline Delay
PIXPHASE1
18 4/7
tLAT3
Figure 53 (LVDS)
TADC
PIXPHASE2
18
Figure 58 (CMOS)
PIXPHASE3
17 4/7
PIXPHASE0
18
2 Channel Mode Pipeline Delay
PIXPHASE1
17 4/7
tLAT2
Figure 54 (LVDS)
TADC
PIXPHASE2
17
Figure 59(CMOS)
PIXPHASE3
16 4/7
PIXPHASE0
16
1 Channel Mode Pipeline Delay
PIXPHASE1
15 4/7
tLAT1
Figure 55 (LVDS)
TADC
PIXPHASE2
15
Figure 60(CMOS)
PIXPHASE3
14 4/7
Mode 3
22
SH out to First Valid Data
tSHFD
Mode 2
21
TADC
(tSHFP + tLATx)
Mode 1
19
SH_R Timing Specifications (Figure 49)
tSHR_S
SH_R Setup Time
1.28
ns
tSHR_H
SH_R Hold Time
2.25
ns
LVDS Output Timing Specifications (Figure 52)
fINCLK = 45MHz
TXvalid
TX Output Data Valid window
INCLK = ADCCLK
2
ns
(ADC Rate Clock)
TXpp0
TXCLK to Pulse Position 0
0.013
ns
TXpp1
TXCLK to Pulse Position 1
3.093
ns
LVDS Output
Specifications not tested in
TXpp2
TXCLK to Pulse Position 2
6.238
ns
production.
TXpp3
TXCLK to Pulse Position 3
9.613
ns
Min/Max ensured by design,
TXpp4
TXCLK to Pulse Position 4
12.663
ns
characterization and statistical
analysis.
TXpp5
TXCLK to Pulse Position 5
15.762
ns
TXpp6
TXCLK to Pulse Position 6
18.982
ns
(1)
Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
12
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