LM98714 datasheet(64/115 Pages) TI1

64 / 115 page

LM98714

SNAS254A – OCTOBER 2006 – REVISED JANUARY 2014

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READING THE SERIAL REGISTERS

To read to the serial registers, the timing diagram shown in Figure 62 must be met. First, SEN is toggled low.

The LM98714 assumes control of the SDIO pin during the first eight clocks of the command. During this period,

data is clocked out of the device at the rising edge of SCLK. The eight bit value clocked out is the contents of the

previously addressed register, regardless if the previous command was a read or a write. At the rising edge of

ninth clock, the LM98714 releases control of the SDIO pin. At the falling edge of the ninth clock period, the

master should assume control of the SDIO pin and begin issuing the new command. SDIO is clocked into the

LM98714 at the rising edge of SCLK. The remaining bits are composed of the “read” command bit (a one), two

device address bits (zeros for the LM98714), five bit register address to be read, and the eight bit “don’t care”

bits. When SEN toggles high, the register is not written to, but its contents are staged to be outputted at the

beginning of the next command.

Figure 62. Serial Read

Serial Interface Timing Details

Figure 63. Serial Interface Specification Diagram

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LM98714 Datasheet(PDF) 64 Page - Texas Instruments