LM98714 datasheet(77/115 Pages) TI1

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LM98714

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SNAS254A – OCTOBER 2006 – REVISED JANUARY 2014

Table 16. (continued)

Address

Default

Page

Bit(s)

Description

(Binary)

Title

(Binary)

[7:0]

Main Configuration Register 1

Source Follower Enable.

[7]

0 Disable (Default)

1 Enable

Input Bias Enable. Enables the Input Bias Resistor ladder.

[6]

0 Disable

1 Enable (Default)

Input Polarity. Configures the polarity mode of the input signal.

[5]

0 Negative going input relative to reference (Default)

1 Positive going input relative to reference

Sampling Mode Select.

[4]

0 Sample and Hold Mode

1 Correlated Double Sampling Mode (Default)

Output Format.

[3]

0 LVDS (Default)

Main

0101

0 0001

Configurati

1 CMOS

0000

on 1

PIXCLK/ADCCLK Configuration. Selects appropriate multiplier for given input clock frequency.

Mode 3: ADC Frequency = 3x Pixel Frequency

Mode 2: ADC Frequency = 2x Pixel Frequency

Mode 1: ADC Frequency = 1x Pixel Frequency

[2]

0 ADCCLK User supplies ADC rate clock, LM98714 performs no multiplication

1 PIXCLK User supplies Pixel rate clock, LM98714 performs clock multiplication

Mode 3: PIXCLK internally multiplied by 3 to get ADC clock

Mode 2: PIXCLK internally multiplied by 2 to get ADC clock

Mode 1: PIXCLK = ADCCLK. This bit is not used for Mode 1

[1:0]

Pixel Phase Clock Select. Coarse adjustment for Pixel phase relative to INCLK. Useful in systems where Pixel

inputs arrive with significant delay relative to INCLK.

00 PIXPHASE0. Pixel phase aligned with INCLK

01 PIXPHASE1. Pixel phase delayed by (TADC Clock* 3/7)

10 PIXPHASE2. Pixel phase delayed by (TADC Clock)

11 PIXPHASE3. Pixel phase delayed by (TADC Clock * (1 + 3/7))

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