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LM98714 Datasheet(PDF) 80 Page - Texas Instruments |
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LM98714 Datasheet(HTML) 80 Page - Texas Instruments |
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80 / 115 page  LM98714 SNAS254A – OCTOBER 2006 – REVISED JANUARY 2014 www.ti.com Table 16. (continued) Address Register Default Page Bit(s) Description (Binary) Title (Binary) [7:0] VCLP Configuration Register [7:6] Reserved VCLP Reference Select. VCLP 00 External Bias (No Internal Connection to Ladder Resistors or DAC) 0010 0 0 0111 Configurati 0000 [5:4] 01 Internal VCLP DAC connection only on 10 Internal Resistor Ladder connection only (Default) 11 Reserved [3:0] 4 Bit nibble for VCLP Reference DAC value. [7:0] Black Level Correction Circuitry Configuration Register Line Averaging. Number of Lines that the correction loop will run. Line Counter is reset during any write to this register. A line beginning is defined by the SH pulse. 00 Infinite (Default) [7:6] 01 15 Lines 10 31 Lines 11 63 Lines Pixel Averaging. Number of Black Level Pixels averaged by the correction loop. 00 4 Pixels [5:4] 01 8 Pixels Black Level 10 16 Pixels 0000 0 0 1000 Clamp 0000 11 32 Pixels Control Offset Integration. 00 Divide by 8 [3:2] 01 Divide by 16 10 Divide by 32 11 Divide by 64 BLKCLP Mode Select. If Auto Black Clamp pulse is enabled, Offset DAC registers are read only. 00 Auto Black Clamp Circuitry Disabled (default) [1:0] 01 Auto Black Clamp pulse delayed from falling edge of SH pulse 10 Auto Black Clamp pulse delayed from falling edge of CLPIN pulse 11 Reserved [7:0] Auto Black Level Clamp Position Register Auto Black Level 0000 [7] Reserved 0 0 1001 Clamp 0000 Black Level Clamp Position. Number of pixels in which Auto Black pulse is delayed, relative to selected trigger [6:0] Position source. 80 Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM98714 |
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