UM0434 datasheet(340/390 Pages) STMICROELECTRONICS

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UM0434

Nexus3 module

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entered, a debug status message is transmitted with DS[31–25]. The external tool can read

this register at any time.

12.4.5

Read/Write access Control/Status register (RWCS)

The read write access control/status register, shown in

Table 227, provides control for

read/write access. Read/write access provides DMA-like access to memory-mapped

resources on the AHB system bus either while the processor is halted, or during runtime.

RWCS also provides read/write access status information; see

Table 229.

Table 225.

Development status register (DS)

31 30

28 27 26 25 24

Field DBG

LPC

LPC CHK

—

Reset

All zeros

R/W

Read–only

Number

0x4

Table 226.

DS field descriptions

Bits

Name

Description

DBG

e200z3 CPU debug mode status

0 CPU not in debug mode

1 CPU in debug mode (

jd_debug_b signal asserted)

30–28

LPS

e200z3 system low power mode status

000 Normal (run) mode

XX1 Doze mode (

p_doze signal asserted)

X1X Nap mode (

p_nap signal asserted)

1XX Sleep mode (

p_sleep signal asserted)

27–26

LPC

e200z3 CPU low power mode status

00 Normal (run) mode

01 CPU in halted state (

p_halted signal asserted)

10 CPU in stopped state (

p_stopped signal asserted)

11 Reserved

CHK

e200z3 CPU checkstop status

0 CPU not in checkstop state

1 CPU in checkstop state (

p_chkstop signal asserted)

24–0

—

Reserved, should be cleared.

Table 227.

Read write access control/status register (RWCS)

31 30 29

2726 242322 21 20

1615

Field

AC RW

MAP

—

CNT

ERR DV

Reset

All zeros

R/W

Read/Write

Number

0x7

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