UM0434 datasheet(338/390 Pages) STMICROELECTRONICS

338 / 390 page

UM0434

Nexus3 module

339/391

12.4.3

Development control register 1, 2 (DC1, DC2)

The development control registers are used to control the basic development features of the

Nexus3 module. Development control register 1 is shown in

Table 221 and its fields are

described in

Table 219.

Table 221.

Development control register 1 (DC1)

29 28 27 26 25

24 23

8 7

5 4 3 2

Field OPC MCK_DIV EOC — PTM WEN

—

OVC EIC

Reset

All zeros

R/W

Read/Write

Number

0x2

Table 222.

DC1 field descriptions

Bits

Name

Description

OPC

Output port mode control

0 Reduced port mode configuration (minimum number of

nex_mdo[n:0] pins

defined by SOC)

1 Full port mode configuration (maximum number of

nex_mdo[n:0] pins

defined by SOC)

30–29

MCK_DIV

MCKO clock divide ratio. See note below.

nex_mcko is 1x processor clock freq.

nex_mcko is 1/2x processor clock freq.

nex_mcko is 1/4x processor clock freq.

nex_mcko is 1/8x processor clock freq.

28–27

EOC

EVTO control

nex_evto_b upon occurrence of watchpoints (configured in DC2)

nex_evto_b upon entry into debug mode

nex_evto_b upon timestamping event

11 Reserved

—

Reserved

PTM

Program trace method

0 Program trace uses traditional branch messages.

1 Program trace uses branch history messages.

WEN

Watchpoint trace enable

0 Watchpoint messaging disabled

1 Watchpoint messaging enabled

23–8

—

Reserved

7–5

OVC

Overrun control

000 Generate overrun messages

001–010 Reserved

011 Delay processor for BTM/DTM/OTM overruns

1XX Reserved

UM0434 Datasheet(PDF) 338 Page - STMicroelectronics

UM0434 Datasheet(HTML) 338 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL