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UM0434 Datasheet(PDF) 339 Page - STMicroelectronics |
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UM0434 Datasheet(HTML) 339 Page - STMicroelectronics |
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339 / 390 page ![]() Nexus3 module UM0434 340/391 Note: OPC and MCK_DIV must be modified only during system reset or debug mode to ensure correct output port and output clock functionality. It is also recommended that all other bits of DC1 be modified only in one of these two modes. Development control register 2 is shown in Table 223 and its fields are described in Table 224. The EOC bits in DC1 must be programmed to trigger EVTO on watchpoint occurrence for the EWC bits to have any effect. 12.4.4 Development status register (DS) The development status registe shown in Table 225 is used to report system debug status. When debug mode is entered or exited, or an SOC- or e200z3-defined low-power mode is 4–3 EIC EVTI control 00 nex_evti_b is used for synchronization (program trace/data trace) 01 nex_evti_b is used for debug request 1XReserved 2–0 TM Trace mode 000No trace 1XXProgram trace enabled X1XData trace enabled XX1Ownership trace enabled Table 222. DC1 field descriptions (continued) Bits Name Description Table 223. Development control register 2 (DC2) 31 24 23 0 Field EWC — Reset All zeros R/W Read/Write Number 0x3 Table 224. DC2 field descriptions Bits Name Description 31–24 EWC EVTO Watchpoint Configuration 00000000No watchpoints trigger nex_evto_b 1xxxxxxxWatchpoint #0 (IAC1 from Nexus1) triggers nex_evto_b x1xxxxxxWatchpoint #1 (IAC2 from Nexus1) triggers nex_evto_b xx1xxxxxWatchpoint #2 (IAC3 from Nexus1) triggers nex_evto_b xxx1xxxxWatchpoint #3 (IAC4 from Nexus1) triggers nex_evto_b xxxx1xxxWatchpoint #4 (DAC1 from Nexus1) triggers nex_evto_b xxxxx1xxWatchpoint #5 (DAC2 from Nexus1) triggers nex_evto_b xxxxxx1xWatchpoint #6 (DCNT1 from Nexus1) triggers nex_evto_b xxxxxxx1Watchpoint #7 (DCNT2 from Nexus1) triggers nex_evto_b 23–0 — Reserved |
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