UM0434 datasheet(342/390 Pages) STMICROELECTRONICS

342 / 390 page

UM0434

Nexus3 module

343/391

Read/write accesses to the AHB require that the debug firmware properly retrieve/place the

data in the RWD.

Table 231 shows the proper placement of data into the RWD. Note that

double-word transfers require two passes through RWD.

Table 232 shows the mapping of RWD bytes to byte lanes of AHB read & write data buses.

Table 230.

read/write access data register

Field

Read/Write Data

Reset

All zeros

R/W

Read/Write

Number

0x9

Table 231.

RWD data placement for transfers

Transfer sizeand byte offset

RWA(2–0)

RWCS[SZ]

RWD

31–24

23–16

15–8

7–0

Byte

x x x

0 0 0

—

Half

x x 0

0 0 1

—

Word

x 0 0

0 1 0

Doubleword

0 0 0

0 1 1

First RWD pass (low order data)

Second RWD pass (high order data)

"X" indicates byte lanes with valid data

“—” indicates byte lanes which will contain unused data.

Table 232.

RWD byte lane data placement

Transfer sizeand

byte offset

RWA(2:0)

RWD

31–24

23–16

15–8

7–0

Byte @000

0 0 0

—

AHB[7–0]

Byte @001

0 0 1

—

AHB[15–8]

Byte @010

0 1 0

—

AHB[23–16]

Byte @011

0 1 1

—

AHB[31–24]

Byte @100

1 0 0

—

AHB[39–32]

Byte @101

1 0 1

—

AHB[47–40]

Byte @110

1 1 0

—

AHB[55–48]

Byte @111

1 1 1

—

AHB[63–56]

Half @000

0 0 0

—

AHB[15–8]

AHB[7–0]

Half @010

0 1 0

—

AHB[31–24]

AHB[23–16]

Half @100

1 0 0

—

AHB[47–40]

AHB[39–32]

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