UM0434 datasheet(337/390 Pages) STMICROELECTRONICS

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Nexus3 module

UM0434

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12.4.2

Port configuration register (PCR)

The port configuration register (PCR) shown in

Table 219 controls the basic port functions

for all Nexus modules in a multiple Nexus environment. This includes clock control and

auxiliary port width. All bits in this register are writable only once after system reset.

Note:

The CSC and PCR registers exist in a separate module at the SoC level in a multiple Nexus

environment. If the e200z3 Nexus3 module is the only Nexus module, these registers are

not implemented and the e200z3 Nexus3-defined development control register 1 (DC1) is

used to control Nexus port functionality.

Table 218.

CSC field descriptions

Bits

Name

Description

7–4

—

Reserved, should be cleared.

3–0

CSC

Client select control

0xX = Nexus client (SoC level)

Table 219.

Port configuration register

26 25

Field

OPC — MCK_EN MCK_DIV

—

Reset

All zeros

R/W

Read/Write

Number

PCR_INDEX

Table 220.

PCR field descriptions

Bits

Name

Description

OPC

Output port mode control

0 Reduced port mode configuration (minimum number of

nex_mdo[n:0] pins

defined by SOC)

1 Full port mode configuration (maximum number of

nex_mdo[n:0] pins

defined by SOC)

—

Reserved

MCK_EN

MCKO clock enable. See note below.

nex_mcko is disabled

nex_mcko is enabled

28–26

MCK_DIV

MCKO clock divide ratio

000

nex_mcko is 1x processor clock freq.

001

nex_mcko is 1/2x processor clock freq.

010 Reserved (default to 1/2x processor clock freq.)

011

nex_mcko is 1/4x processor clock freq.

100–110 Reserved (default to 1/2x processor clock freq.)

111

nex_mcko is 1/8x processor clock freq.

25–0

—

Reserved

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