UM0434 datasheet(387/390 Pages) STMICROELECTRONICS

387 / 390 page

Glossary

UM0434

388/391

Snooping. Monitoring addresses driven by a bus master to detect the need for coherency

actions.

Snoop push. Response to a snooped transaction that hits a modified cache block. The

cache block is written to memory and made available to the snooping device.

Split-transaction. A transaction with independent request and response tenures.

Split-transaction bus. A bus that allows address and data transactions from different

processors to occur independently.

Stage. The term

stage is used in two different senses, depending on whether the pipeline is

being discussed as a physical entity or a sequence of events. In the latter case, a stage is an

element in the pipeline during which certain actions are performed, such as decoding the

instruction, performing an arithmetic operation, or writing back the results. Typically, the

latency of a stage is one processor clock cycle. Some events, such as dispatch, write-back,

and completion, happen instantaneously and may be thought to occur at the end of a stage.

An instruction can spend multiple cycles in one stage. An integer multiply, for example, takes

multiple cycles in the execute stage. When this occurs, subsequent instructions may stall.

An instruction may also occupy more than one stage simultaneously, especially in the sense

that a stage can be seen as a physical resource—for example, when instructions are

dispatched they are assigned a place in the CQ at the same time they are passed to the

execute stage. They can be said to occupy both the complete and execute stages in the

same clock cycle.

Stall. An occurrence when an instruction cannot proceed to the next stage.

Static branch prediction. Mechanism by which software (for example, compilers) can hint

to the machine hardware about the direction a branch is likely to take.

Store Queue. Holds store operations that have not been committed to memory, resulting

from completed or retired instructions.

Superscalar. A superscalar processor is one that can dispatch multiple instructions

concurrently from a conventional linear instruction stream. In a superscalar implementation,

multiple instructions can be in the same stage at the same time.

Supervisor mode. The privileged operation state of a processor. In supervisor mode,

software, typically the operating system, can access all control registers and can access the

supervisor memory space, among other privileged operations.

Synchronization. A process to ensure that operations occur strictly

in order. See Context

synchronization and Execution synchronization.

Synchronous interrupt. An

interrupt that is generated by the execution of a particular

instruction or instruction sequence. There are two types of synchronous interrupts,

precise

and

imprecise.

System memory. The physical memory available to a processor.

TLB (translation lookaside buffer). A cache that holds recently-used

page table entries.

Throughput. The number of instructions that are processed per clock cycle.

UM0434 Datasheet(PDF) 387 Page - STMicroelectronics

UM0434 Datasheet(HTML) 387 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL