UM0434 datasheet(384/390 Pages) STMICROELECTRONICS

384 / 390 page

UM0434

Glossary

385/391

Mantissa. The decimal part of a logarithm.

Memory access ordering. The specific order in which the processor performs load and

store memory accesses and the order in which those accesses complete.

Memory-mapped accesses. Accesses whose addresses use the page or block address

translation mechanisms provided by the MMU and that occur externally with the bus

protocol defined for memory.

Memory coherency. An aspect of caching in which it is ensured that an accurate view of

memory is provided to all devices that share system memory.

Memory consistency. Refers to agreement of levels of memory with respect to a single

processor and system memory (for example, on-chip cache, secondary cache, and system

memory).

Memory management unit (MMU). The functional unit that is capable of translating an

effective (logical) address to a physical address, providing protection mechanisms, and

defining caching methods.

Most-significant bit (msb). The highest-order bit in an address, registers, data element, or

instruction encoding.

Most-significant byte (MSB). The highest-order byte in an address, registers, data

element, or instruction encoding.

NaN. An abbreviation for not a number; a symbolic entity encoded in floating-point format.

There are two types of NaNs—signaling NaNs and quiet NaNs.

No-op. No-operation. A single-cycle operation that does not affect registers or generate bus

activity.

Normalization. A process by which a floating-point value is manipulated such that it can be

represented in the format for the appropriate precision (single- or double-precision). For a

floating-point value to be representable in the single- or double-precision format, the leading

implied bit must be a 1.

Optional. A feature, such as an instruction, a register, or an interrupt, that is defined by the

PowerPC architecture but not required to be implemented.

Out-of-order. An aspect of an operation that allows it to be performed ahead of one that

may have preceded it in the sequential model, for example, speculative operations. An

operation is said to be performed out-of-order if, at the time that it is performed, it is not

known to be required by the sequential execution model. See

In-order.

Out-of-order execution. A technique that allows instructions to be issued and completed

in an order that differs from their sequence in the instruction stream.

Overflow. An condition that occurs during arithmetic operations when the result cannot be

stored accurately in the destination register(s). For example, if two 32-bit numbers are

multiplied, the result may not be representable in 32 bits. Because 32-bit registers cannot

represent this sum, an overflow condition occurs.

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