UM0434 datasheet(383/390 Pages) STMICROELECTRONICS

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Glossary

UM0434

384/391

addition, for 32-bit implementations, instructions that are defined only for 64-bit

implementations are considered to be illegal instructions. For 64-bit implementations

instructions that are defined only for 32-bit implementations are considered to be illegal

instructions.

Implementation. A particular processor that conforms to the PowerPC architecture, but

may differ from other architecture-compliant implementations for example in design, feature

set, and implementation of

optional features. The PowerPC architecture has many different

implementations.

Imprecise interrupt. A type of

synchronous interrupt that is allowed not to adhere to the

precise interrupt model (see

Precise interrupt). The PowerPC architecture allows only

floating-point exceptions to be handled imprecisely.

Instruction queue. A holding place for instructions fetched from the current instruction

stream.

Integer unit. The functional unit in the processor responsible for executing all integer

instructions.

In-order. An aspect of an operation that adheres to a sequential model. An operation is

said to be performed in-order if, at the time that it is performed, it is known to be required by

the sequential execution model. See

Out-of-order.

Instruction latency. The total number of clock cycles necessary to execute an instruction

and make ready the results of that instruction.

Interrupt. A condition encountered by the processor that requires special, supervisor-level

processing.

Interrupt handler. A software routine that executes when an interrupt is taken. Normally,

the interrupt handler corrects the condition that caused the interrupt, or performs some other

meaningful task (that may include aborting the program that caused the interrupt).

Kill. An operation that causes a

cache block to be invalidated without writing any modified

data to memory.

Latency. The number of clock cycles necessary to execute an instruction and make ready

the results of that execution for a subsequent instruction.

L2 cache. See

Secondary cache.

Least-significant bit (lsb). The bit of least value in an address, register, field, data

element, or instruction encoding.

Least-significant byte (LSB). The byte of least value in an address, register, data element,

or instruction encoding.

Little-endian. A byte-ordering method in memory where the address

n of a word

corresponds to the

least-significant byte. In an addressed memory word, the bytes are

ordered (left to right) 3, 2, 1, 0, with 3 being the

most-significant byte. See Big-endian.

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